Method of stabilizing reference bit of multi-bit memory cell

Details Method of stabilizing reference bit of multi-bit memory cell Method of stabilizing reference bit of multi-bit memory cell

2001-11-13

2002-10-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S210130

Reexamination Certificate

active

06466477

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90127397, filed Nov. 5, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of stabilizing a reference bit, and more particularly, to a method of stabilizing a reference bit of a multi-bit memory cell.
2. Description of the Related Art
The NROM is a memory structure that can store two bits in one memory cell. One or more memory cells are used as reference cells for either the typical memory chip or the NROM array chip. The current obtained by reading the reference bit of the reference memory cell can be used as a comparison reference for reading other memory cells in the same memory. However, while reading the reference bit in the reference cell in the prior art, a few electrons may tunnel through the oxide layer and stay in the floating gate due to the channel hot electron effect. Thus, the current obtained by reading the reference cell is different from the required current.
FIG. 1
shows the structure of a conventional NROM memory.
Voltages are respectively applied to the gate
11
and the source/drain region (
2
)
16
to read the reference bit (bit
1
) of the floating gate
13
. When the reference bit (bit
1
) is low, a channel is formed between the source/drain region (
2
)
16
and the source/drain region (
1
)
15
. The current flows from the source/drain region (
1
)
15
to the source/drain region (
2
)
16
. When the reference bit (bit
1
) is high, the high electric field around the source/drain region (
2
)
16
of the NROM
10
shuts the channel. There is no current flowing between the source/drain region (
2
)
16
and the source/drain region (
1
)
15
. When there is a current flowing through the channel, the carrier in the channel is accelerated to cause a series of bombardments. After bombarding with the silicon lattice, an electron-hole pair is generated. The electron and hole are further accelerated by the electric field to cause another order of bombardment. The high-energy carriers thus have great opportunity to tunnel through the first oxide layer
14
and stay in the nitride layer
13
. This is the process for programming the reference bit (bit
1
).
After reading the NROM
10
several times, the electrons accumulate in the position where the reference bit (bit
1
) is located in the nitride layer
13
. The current becomes unstable while reading the reference bit (bit
1
). It cannot be compared to the stored data in other memory cells correctly. The reference bit is thus meaningless.
SUMMARY OF THE INVENTION
The invention provides a method of stabilizing a reference bit of a multibit memory cell. The voltage of the reference bit of the multi-bit memory cell is effectively maintained in a stable state even after several reading processes. The current obtained by reading the reference bit is also stabilized.
In the method of stabilizing the reference bit of the multi-bit memory cell, a first bit is pre-programmed to high during fabrication. The rest of the bits excluding the first bit are then used as reference bits while reading the memory cell.
According to the above, the first bit of the reference memory cell is programmed to high, so that the threshold voltage of reference bit is stabilized. Consequently, the process of reading the reference bit is not affected by electron tunneling and the current is stable.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5091888 (1992-02-01), Akaogi
patent: 5615153 (1997-03-01), Yiu et al.
patent: 6160737 (2000-12-01), Hsu et al.
patent: 6188604 (2001-02-01), Liu et al.
patent: 6262916 (2001-07-01), Kuriyama et al.
U.S. patent publication application US 2001/0048614 By Bloom et al.

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