Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-12-20
2004-08-31
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000, C327S163000
Reexamination Certificate
active
06784706
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to phase-locked loops, and in particular to a method of stabilizing phase-locked loops referred to herein as a lock aid.
2. Description of Related Art
In a phase-locked loop (PLL), an important design criterion is the response of the PLL to phase and frequency jumps. Such jumps can occur in many situations. A typical situation is the start-up phase when the operating frequency has not been attained and the PLL is not in phase lock. In wireless applications the frequency may be sufficiently accurate, for instance after receiving a number of bursts in TDMA traffic, that the frequencies are quite well aligned. But the chances are, when a new burst is received, that the phase will not in alignment.
PLLs are not only used in telecommunications applications, but also in measurement technology (for instance optical telemetry), control of motors (both electrical and regular fuel), medical equipment and the like. Also in those applications the phase and frequency step responses are important design criteria.
The response of a PLL depends on the type of PLL. An important class of PLL is the type II PLL, in which the loop filter contains both an integrating part and a proportional part. The integrating part ensures that the PLL does not convert frequency errors into phase errors. As long as the phase difference is not zero, the integrator pushes the PLL in the direction tending to make the phase difference zero. This is critical for many applications such as motor control, telecom applications, and measurement applications. There are applications that are not hampered too much by not having the integrator in the loop filter, but those are relatively few.
FIG. 1
shows a typical type II PLL. In the Figure CO stands for Controlled Oscillator. This could be any kind of suitable oscillator, such as a voltage controlled, current controlled, or digital controlled oscillator. The PLL also consists of a pure integrator; the VCO, CCO, or DCO; and a sampling element in the phase detector. The loop proportional unit is needed to stabilize the PLL. In conventional PLLs this is quite often implemented as an extra zero next to the pole of the loop filter. The schematic that is probably the most common is shown in FIG.
2
. In this figure the resistor and the capacitor together form the filter, where the capacitor forms, together with the current output of the charge pump phase detector, a pure integrator. The resistor creates the extra zero in the loop filter.
The I and P factors are known in the art and control the performance of the PLL. The output of the integrator is added to the output of the phase detector multiplied by the P factor to determine the frequency of the controlled oscillator. When the phase difference is zero, i.e. on a phase hit, the frequency of the controlled oscillator is determined by the output of the integrator.
The integrator in the loop may in fact be a sampled integrator, a summator or accumulator. Such a structure does not significantly affect design considerations. At relatively high bandwidths the exact behaviour changes slightly due to the sampling. In such a case use of the modified Z transformation may be necessary. This is shown as an alternative configuration in FIG.
3
.
The combination of zero and pole in the filter is not necessarily stable in all aspects. If the system is overdamped, the response to errors will have some overshoot, but will not show oscillatory properties. If it is underdamped, it will show oscillatory properties, which may or may not converge. The overshoot, whether oscillatory or not, will always show in the spectral performance of the whole PLL as peaking. This is the point in the transfer where the transfer does not attenuate, but amplifies, albeit only slightly with proper settings.
Thus, it will be seen that a type II PLL will show overshoot in the time domain, and show some peaking in the frequency domain, unless the integrating part always yields zero, in which case the PLL degenerates into a type I PLL, which is associated with its own set of problems.
FIG. 4
shows the overshoot as a result of variable damping with a normalized low pass corner frequency of 1 rad/s. The curve with damping 1.01 is more or less critically damped. Damping equal to 0.5 (underdamped) yields a large overshoot and some oscillatory behaviour. Damping equal to 2 is considered overdamped.
FIG. 5
shows the transfer (in dB's vertically) with peaking as a result of variable with a normalized corner frequency of 1 rad/s (about 0.16 Hz). Although poorly visible, the overdamped case (damping is 2) exhibits peaking.
For the best lock behaviour it is important for the response converge as fast as possible to the final situation. At the same time, such speedy convergence requires a relatively aggressive setting of the integrator, which makes the overshoot and peaking relatively large. In many applications this is not acceptable; in mechanical applications, such as the control of a bridge, such overshoot, together with the non-linear aspects of the pilons the bridge hangs on, could cause oscillatory effects in the bridge itself, which could create tremendous damage. In the case of telecom networks overshoot and peaking might accumulate through the network. Such accumulation could yield unacceptable peaking and overshoot at end nodes, so that equipment would start to fail. In fact, if the network is not completely under control (and the complexity of modern networks is too high to be really completely under control) a partial blackout might occur due to the peaking phenomenon. But such blackout can cause other parts of the network to exhibit the same kind of accumulative behaviour, so that after some time the whole network is blacked out. The economic consequences of such as scenario would be catastrophic. So, it is of importance to limit peaking and overshoot. In existing standards for telecom, typical numbers that may be encountered are for instance 0.2 dB peaking, or 0.5 dB peaking maximum. These numbers are quite small.
The effect of these numbers is that the frequency and phase jump response are influenced. In such responses two major time constants can be distinguished, one for the initial response, another for the longer term settling part. These are shown as I and II in FIG.
6
. The actual behaviour is more complex than can be represented by two time constants. However, for the purposes of discussion the use of the two time constants is sufficient.
Careful mathematical study of the formulas that apply to phase and frequency jumps shows that the ratio between the time constants depends on, or is coherent with, the peaking and overshoot behaviour. For instance, if peaking is limited to 0.2 dB, the second time constant is at least about 50 times the first time constant. This is true for both frequency and phase locking, which more or less exhibit identical behaviour. This is to be expected since the phase is the integral of frequency and all transfer curves of such a system are exponential in nature.
It might be thought that actual frequency behaviour is much worse than the phase behaviour in view of the fact that a frequency error will rapidly build up a large phase error, whereas a phase error is of course limited. However, a transfer curve is not affected significantly by the size of the data to be transferred but rather by the attenuation and the like.
The observed ratio between the two time constants can be explained in relative terms for the integrating and the proportional part; if the proportional part has not reached zero, there still is a phase error, which will make the integrating part change. The integrator setting must be insensitive, so that peaking and overshoot remain limited. Thus the integrator will not fill fast. However, the quantity that the integrator gains is more or less lost by the proportional part once the frequency is in lock. Thus it could be said that the long term settling is defined by the bleeding of the proportional part into the integrating part. Si
de Rijk Johannes Hermanus Aloysius
Van Der Valk Robertus Laurentius
Callahan Timothy P.
Laubscher, Jr. Lawrence E.
Nguyen Hai L.
Zarlink Semiconductor Inc.
LandOfFree
Method of stabilizing phase-locked loop does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of stabilizing phase-locked loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of stabilizing phase-locked loop will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3330671