Method of spare capacity use for fault detection in a multiproce

Details Method of spare capacity use for fault detection in a multiproce Method of spare capacity use for fault detection in a multiproce

1987-03-18

1989-02-21

Atkinson, Charles E.

Excavating

371 68, 364200, G06F 1120

Patent

active

048072281

ABSTRACT:
A method of detecting and identifying faulty processors in a multiprocessor system. A processing task is assigned when possible to two processors, a primary processor and a secondary processor if a second idle processor is available. In one embodiment, the operations of a secondary processor are preempted and that processor is reassigned as primary for another task if no idle processor is available when the task is initiated. In a second embodiment, the operations of a secondary processor are not preempted, and a new task is queued until an idle processor becomes available. If a secondary processor completes a task, its results are compared with the results of the primary processor. Disagreement messages are broadcast to a central controller in a nondistributed embodiment and to all the processors in the system in a distributed embodiment. The disagreement messages are periodically analyzed by the controller or by each processor. In the distributed embodiment, the analysis algorithm is such that each nonfaulty processor identifies the same subset of faulty processors.

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W. R. Moore, "Fault Detection and Correction in Array Computers for Image Processing", IEEE Proceedings, vol. 129, Pt. E, No. 6, Nov. 1982, pp. 229-234.

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