Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-04-26
2011-04-26
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S136000
Reexamination Certificate
active
07934185
ABSTRACT:
A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
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Ballagh Jonathan B.
Hwang L. James
Milne Roger Brent
Shirazi Nabeel
Stroomer Jeffrey D.
Cuenot Kevin T.
Dinh Paul
Xilinx , Inc.
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