Method of shrinking semiconductor mask features for process...

Details Method of shrinking semiconductor mask features for process... Method of shrinking semiconductor mask features for process...

2011-08-30

2011-08-30

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

C716S051000, C716S052000, C716S053000, C716S054000, C716S055000, C716S056000

Reexamination Certificate

active

08010912

ABSTRACT:
Provided is a method to design an integrated circuit. The method reduces a time delay between introduction of a new lithography process and a start of production. A first semiconductor mask is designed at a first process feature size. The first process feature size can be based on an anticipated process feature size of the new lithography process. A second semiconductor mask is created by enlarging the first semiconductor mask to a second process feature size for which production is available. Thus, the second process feature size is larger than the first process feature size. An integrated circuit (IC) is fabricated with the second semiconductor mask. After the new semiconductor process has been developed and is available for production, another IC is fabricated with the first semiconductor mask.

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