Method of shallow trench isolation formation and planarization

Details Method of shallow trench isolation formation and planarization Method of shallow trench isolation formation and planarization

2001-06-19

2003-09-09

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000

Reexamination Certificate

active

06617251

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to shallow trench isolation (STI) processes employed in the fabrication of integrated circuits (ICs). The present invention more particularly relates to an improved process for the formation and planarization of shallow trench isolated devices (henceforth referred to as STIs) without the use of chemical mechanical planarization (CMP).
2. Description of the Related Art
As IC technology has moved to smaller feature sizes and the density of IC features in an IC substrate surface increases, STI processes have replaced the local oxidation of silicon (LOCOS) isolation methods as the process of choice for isolating active areas in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, for example. Local oxidation of silicon (LOCOS) isolation methods are undesirable at sub-0.5 &mgr;m dimensions and lower because they typically introduce non-planarity and a “bird's beak” at the edge of an active area and therefore reduce the packing density of the circuitry. In contrast, STI processes provide isolation schemes that produce a relatively high degree of planarity and eliminate the bird's beak to dramatically reduce the chip area required for isolation.
FIGS. 1A-C
show some major steps of a conventional STI process that may be employed to fabricate trenches in the IC substrate. In order to form a partially fabricated IC substrate
10
(hereinafter referred to as “IC substrate”) as shown in
FIG. 1A
, a pad oxide layer
24
, e.g., a silicon dioxide layer, is blanket deposited or grown on a surface of an IC substrate layer
12
. A polishing stopping mask layer
14
, e.g., a silicon nitride layer (Si
3
N
4
), is then blanket deposited over pad oxide layer
24
.
Next, polishing stopping layer
14
, pad oxide layer
24
and IC substrate layer
12
are etched through using conventional photolithography and etch techniques well known to those skilled in the art to form trenches
18
,
20
and
22
in IC substrate layer
12
. Trench
22
is formed in a relatively wide open area in which relatively wide active areas, also referred to as wide diffusion areas or wide island areas, are isolated by relatively wide STIs, and trenches
18
and
20
are formed in a relatively dense area of IC substrate
10
. The dense area, as shown in
FIG. 1A
, has a greater number of trenches per unit area of the IC substrate surface than the wide open area.
Following trench formation, the trenches are typically cleaned using combinations of conventional dry and wet chemistry and the trench side walls oxidized to form a liner, typically a few hundred Angstroms thick, to repair any damage caused by the plasma used in etching the trench. Typically, a few 100 A can be grown wet or dry, with or without HCL. This oxide liner also provides a base for the subsequent insulation deposition.
Then an insulating layer
16
, e.g., a silicon dioxide layer, is deposited, for example by chemical vapor deposition (CVD), high density plasma (HDP) deposition, or spin-on glass (SOG), on the IC substrate
10
filling trenches
18
,
20
and
22
with the insulating layer so that subsequently formed active areas in IC substrate
10
are electrically isolated from each other. As shown in
FIG. 1A
, a portion of insulating layer
16
is also deposited above polishing stopping layer
14
and this portion of insulating layer
16
is referred to as the “insulating layer overburden.”
IC substrate
10
is then subject to chemical-mechanical polishing (CMP) to remove the insulating layer overburden and polishing stopping layer
14
. CMP typically involves mounting an IC substrate on a holder and rotating the IC substrate face against a rotating polishing pad. Those skilled in the art will recognize that because insulating layer
14
typically includes SiO
2
, “oxide CMP” (which refers to the CMP process for polishing SiO
2
) is typically carried out in this step. During oxide CMP, a slurry composition is introduced between the polishing pad and an IC substrate surface.
Variations of this conventional processing exist including the use of a trench planarization mask to expose certain areas of the insulator overburden to etching prior to the CMP planarization. The trench planarization or “reverse” mask is typically generated from the existing active area definitions by a series of logical operations which include undersizing the generated reverse layer to be completely inside the underlying active area for all process conditions including, but not limited to, photolithography misalignment and CD targets. The result of this reverse/trench planarization etch step is a small but uniform amount of insulator in all regions making, in general, the overall polishing, and in particular, the polishing of wide active areas, faster and more reliable. Also, densification of the deposited oxide fill to improve the film quality can be done in an inert atmosphere, or in oxygen, in which case the liner oxidation may be bundled into this densification step.
FIG. 1B
shows an intermediate structure that is formed during oxide CMP after the insulating layer overburden is removed and polishing stopping layer
14
is exposed. The resulting profile of the insulator layer
16
plays an important role in device characteristics including, but not limited to, isolation and well characteristics. Generally, the top of insulator layer
16
after CMP, is designed to be above the top of pad oxide layer
24
so as to prevent uncontrolled “pad oxide undercut” during subsequent processing steps. This pad oxide undercut could result in undesirable device variation.
As shown in
FIG. 1B
, after the insulating layer overburden is removed, the surface of insulating layer
16
above trenches
18
and
20
is substantially planar. Above trench
22
, however, near or about a middle region of the surface of insulating layer
16
(in the wide open area), a concave or indented region
26
may be formed. Concave region
26
recesses inwardly into the surface of insulating layer
16
and is referred to as “dishing” because the profile of the concave region resembles the profile of a dish. The degree of dishing can be quantified by measuring the distance between the center of the surface of insulating layer
16
(above trench
22
), which is typically the lowest point of the concave region, and the point where the insulating layer levels off, which is typically the highest point of the concave region.
After oxide CMP has concluded and polishing stopping layer
14
is removed, isolation structures (i.e., trenches
18
,
20
and
22
filled with insulating material
16
) are formed below the IC substrate layer
12
surface. A pad oxide layer
24
, with the appropriate thickness, is maintained above the IC substrate layer surface and the substantially planar surface of insulating layer
16
above trenches
18
and
20
is preserved, as shown in FIG.
1
C. The degree of dishing, however, in the wide open area above trench
22
may increase and the resulting concave region shown in
FIG. 1C
by reference numeral
26
′ may recess inwardly into the surface of insulating layer
16
to a greater extent because during oxide CMP a material removal rate of the insulating layer (e.g., SiO
2
) is higher than a material removal rate of the polishing stopping layer (e.g., Si
3
N
4
). Thus, oxide CMP has a high selectivity to the polishing stopping layer. After the isolation structures shown in
FIG. 1C
are formed the IC fabrication process typically proceeds to forming IC features of active areas, e.g., transistor devices.
Unfortunately, the conventional STI process described above can lead to device behaviors that are not uniform across the wafer/die, leading to pattern dependence. By way of example, the undesirable dishing effect described above can lead to device behaviors (including, but not limited to, total implants received by the well) to vary according to pattern density. Another problem is the presence of “poly stringers,” remnants of deposited polysilicon, that could not be removed effic

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