Method of shallow trench isolation fill-in without...

Details Method of shallow trench isolation fill-in without... Method of shallow trench isolation fill-in without...

2003-04-28

2004-06-22

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S296000, C438S435000, C438S745000, C438S749000

Reexamination Certificate

active

06753237

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of shallow trench isolation fill-in, and more particularly to a method of shallow trenches isolation fill-in without generation of void.
2. Description of the Related Art
In the manufacturing process of semiconductor device, shallow trench isolation (STI) is a common technique used to prevent unwanted interactions between the circuit elements of semiconductor device. Since the advanced semiconductor technology increases the integration of the circuit elements and interconnection on a silicon substrate (or a wafer), the trench aspect ratio, typically defined as the trench height divided by the trench width, is increased. Therefore, it becomes more difficult to fill in the narrow trench with an insulating material, and the unwanted voids could be generated in the trench so that the insulating function of insulating material fails.
Currently, high density plasma (HDP) oxide deposition is used to fill the trenches, especially the trenches with high aspect ratio. FIG.
1
A~
FIG. 1F
schematically illustrate a conventional trench formation and high density plasma (HDP) oxide fill-in process. As shown in
FIG. 1A
, a silicon substrate
100
is provided first, and then a silicon oxide layer
102
is deposited on the silicon substrate
100
followed by the deposition of a silicon nitride layer
104
on the silicon oxide layer
102
. Next, a photo-resist (PR) layer is deposited on the silicon nitride layer
104
, and etched according to a photo-mask with a predetermined pattern to form a photo-resist (PR)-patterned layer
106
, as shown in FIG.
1
B. Then, the silicon oxide layer
102
and the silicon nitride layer
104
are etched according to the PR-patterned layer
106
, as shown in FIG.
1
C. The PR-patterned layer
106
is removed after etching. Some of silicon loss may occur and create the recesses
108
on the silicon substrate
100
.
Subsequently, the silicon substrate
100
is etched to form the trenches
110
, as shown in
FIG. 1D. A
conventional plasma dry etching process, such as reactive ion etch (RIE), is used to carve the silicon substrate
100
to form the trenches
110
. During the RIE process, the surfaces of the trenches
110
will be damaged by ion bombardment. These damages can be repaired by forming a liner oxide layer
112
on the interior surfaces of the trenches
110
, as shown in FIG.
1
E. The interior surfaces of the trenches
110
can be oxidized by thermal oxidation process to form the liner oxide layer
112
. Then, high density plasma (HDP) oxide fill-in process is performed. After a high density plasma (HDP) oxide layer
114
is deposited, a void
116
could be created in the trench
110
due to sidewall re-deposition, as shown in FIG.
1
F.
Generally, a thin liner oxide layer
112
is obtained according to the above mentioned method, and the thickness thereof is about a couple of hundred angstroms. However, in some of manufacturing processes, a thicker liner oxide layer is required to improve the electrical characteristics of semiconductor device.
Please refer to FIG.
2
A~
FIG. 2D
, another conventional trench formation and high density plasma (HDP) oxide fill-in process. Before the step of
FIG. 2A
, steps similar to those of FIG.
1
A~
FIG. 1C
are carried out. As shown in
FIG. 2A
, an oxide layer
202
is further deposited over the silicon substrate
100
after formation of PR-patterned layer
106
(FIG.
1
C). Then, a plurality of spacers
204
are formed at the sidewalls of SiO—SiN blocks, as shown in FIG.
2
B. The silicon substrate
100
is carved by dry etching process to form the trenches
210
, and the interior surfaces of the trenches
210
are oxidized by thermal oxidation process to form the liner oxide layer
212
, as shown in FIG.
2
C.
Although the thicker liner oxide has a positive effect on the reliability of device, the thicker liner oxide layer has narrowed the width of trench so as to increase the high density plasma (HDP) oxide sidewall redeposition. That makes the high density plasma (HDP) oxide fill-in more difficult. After a high density plasma (HDP) oxide layer
214
is deposited, a void
216
is created in the trench
210
, as shown in FIG.
2
D.
Thus, there remains a need for trench-filling process that provides the void-free feature to ensure the insulating function of insulating material such as high density plasma (HDP) oxide.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of shallow trench isolation fill-in, so as to create the void-free trench after filled with the isolating material.
The invention achieves the above-identified objects by providing a method of shallow trench isolation fill-in, wherein a silicon substrate having a plurality of trenches is provided. First, a liner oxide layer is formed in the trenches. Next, the silicon substrate is pre-wetted with deionized (DI) water; and the liner oxide layer is etched by a chemical solution. The chemical solution is an oxide etchant, such as hydrofluoric acid (HF) solution or buffered oxide etchant (BOE). The etching rate close to an opening of a trench is faster than the etching rate close to a bottom of the trench. Finally, the trenches are filled with a high density plasma (HDP) oxide layer. According to the invention, the prewet-chemical treatment does widen the opening of the trench, so that no void is generated after the trench is filled with the high density plasma (HDP) oxide.


REFERENCES:
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5578518 (1996-11-01), Koike et al.
patent: 5712185 (1998-01-01), Tsai et al.
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 5956598 (1999-09-01), Huang et al.
patent: 6391493 (2002-05-01), Goodenough et al.
patent: 2003/0119256 (2003-06-01), Dong et al.

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