Method of setting phase locked loops by comparing output signals

Details Method of setting phase locked loops by comparing output signals Method of setting phase locked loops by comparing output signals

1993-05-14

1994-10-18

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 17, 331 18, 331 25, 455260, H03L 7093, H03L 716, H03L 710, H03L

Patent

active

053572157

ABSTRACT:
A PLL has at least two attenuators supplying output signals, and a phase detector comparing the output signals of the at least two attenuators. The phase detector has an input and an output stage supplying an output variable being dependent on a phase difference at the input to the phase detector and being influenceable by a further electrical variable. A change in the attenuator ratios of the at least two attenuators takes place synchronously with the existing phase difference. A method for adjusting PLL parameters in the PLL includes synchronously varying the further variable determining the output variable of the phase detector, upon a change in the attenuator ratios.

REFERENCES:
patent: 5153530 (1992-10-01), Takagi et al.
patent: 5208546 (1993-05-01), Nagaraj et al.
patent: 5220294 (1993-06-01), Ichikawa
Publication: Mikroelektronik, vol. 41, No. 1, (1988), pp. 24-28, "C-MOS-PLL-Baustein fur 900-MHz-Funkgerate"; Krings, G. et al.

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