Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2006-02-21
2006-02-21
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000
Reexamination Certificate
active
07002397
ABSTRACT:
In a MOS circuit comprising a plurality of MOSFETs constituting a digital circuit, an input signal is supplied to the digital circuit, and a first back bias voltage is supplied to a semiconductor substrate or a semiconductor well region in which the MOSFETs are formed, so that a pn junction between the semiconductor substrate or the semiconductor well region and a source region is brought to a forward voltage. In a non-operating state in which a circuit operation is suspended by the input signal supplied to the digital circuit as a fixed level, a second back bias voltage is applied to the semiconductor substrate or the semiconductor well region so that the pn junction between the semiconductor substrate or the semiconductor well region and the source region is brought to a reverse voltage.
REFERENCES:
patent: 5483152 (1996-01-01), Hardee et al.
patent: 5557231 (1996-09-01), Yamaguchi et al.
patent: 5570005 (1996-10-01), Hardee et al.
patent: 5583457 (1996-12-01), Horiguchi et al.
patent: 5592010 (1997-01-01), Kakumu et al.
patent: 5659517 (1997-08-01), Arimoto et al.
patent: 5814899 (1998-09-01), Okumura et al.
patent: 5838047 (1998-11-01), Yamauchi et al.
patent: 1-206661 (1989-08-01), None
patent: 3-23591 (1991-01-01), None
patent: 3-136365 (1991-06-01), None
patent: 4-18762 (1992-01-01), None
patent: 5-108194 (1993-04-01), None
patent: 6-21443 (1994-01-01), None
patent: 6-53496 (1994-02-01), None
patent: 6-89574 (1994-03-01), None
patent: 6-216346 (1994-08-01), None
patent: 6-237164 (1994-08-01), None
patent: 6-282987 (1994-10-01), None
patent: 8-83487 (1996-03-01), None
patent: 8-204140 (1996-08-01), None
patent: 8-274620 (1996-10-01), None
patent: 9-8645 (1997-01-01), None
patent: 9-36246 (1997-02-01), None
patent: 9-214321 (1997-08-01), None
patent: 10-189883 (1998-07-01), None
Yamamoto, Toyoji, et al. “A New CMOS Structure for Low Temperature Operation with Forward Substrate Bias,” IEEE 1992 Symposium on VLSI Technology, Digest of Technical Papers, 1992, pp. 104-105.
Sato, Katusyuki et al., “A 20ns Static Column 1 Mb DRAM in CMOS Technology,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1985, pp. 254-255.
Hiraki Mitsuru
Ikeda Syuji
Kubo Masaharu
Mizuno Hiroyuki
Miles & Stockbridge P.C.
Renesas Technology Corp.
Wells Kenneth B.
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