Method of semiconductor via testing

Details Method of semiconductor via testing Method of semiconductor via testing

2005-02-22

2005-02-22

Jackson, Jerome (Department: 2815)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Including isolation structure

C438S430000, C438S622000, C438S629000, C438S637000, C438S639000, C438S640000, C438S687000, C438S668000, C438S672000, C438S700000, C438S701000, C438S713000

Reexamination Certificate

active

06858511

ABSTRACT:
A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.

REFERENCES:
patent: 5962341 (1999-10-01), Ito
patent: 6107185 (2000-08-01), Lukanc
patent: 6211569 (2001-04-01), Lou
patent: 6221780 (2001-04-01), Greco et al.
patent: 6316833 (2001-11-01), Oda

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