Method of semiconductor device isolation

Details Method of semiconductor device isolation Method of semiconductor device isolation

2002-09-12

2004-10-26

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S524000

Reexamination Certificate

active

06809006

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of semiconductor device isolation, and more particularly to a method of semiconductor device isolation, which can minimize design rule of an active region between trenches formed at an isolation region of a semiconductor device.
2. Description of the Prior Art
Semiconductor devices formed on a silicon wafer include a device isolation region serving to electrically isolate circuit patterns from each other. The formation of the device isolation region is an initial process in all fabrication processes, and has an influence upon the size of active regions and upon the process margin in subsequent processes. Thus, as semiconductor devices become more highly integrated and sized down, actively conducted studies to reduce a size of the respective devices and also to reduce the device isolation region are being conducted.
Generally, the LOCOS method, widely used in fabrication of semiconductor devices, is advantageous in that it utilizes a simple process. In a highly integrated semiconductor device of the 256 Megabit DRAM level or above, however, the LOCOS method has limitations due to punch-through by the bird's beak that results from a reduction in width of the device isolation region, as well as a reduction in the thickness of the device isolation film.
For this reason, a device isolation method using trenches, such as the Shallow Trench Isolation (STI) process, were proposed as a technology suitable for device isolation in highly integrated semiconductor devices.
FIGS. 1A
to
1
D illustrate in cross-sectional views the method steps showing a method of semiconductor device isolation according to the prior art.
As shown in
FIG. 1A
, the method of semiconductor device isolation includes applying a photoresist film on a semiconductor substrate
100
where a device isolation region (not shown) was previously defined. The photoresist film is then exposed to light and developed, thereby forming a photoresist pattern (PR)
102
through which the device isolation region is exposed.
In
FIG. 1A
, al represents the minimum design rule of active region between trenches
104
that is capable of being defined using the existing photo equipment, and has a dimension far greater than 0.1 &mgr;m.
Thereafter, the substrate
100
is etched according to the STI process using the photoresist pattern (PR)
102
as a mask, thereby forming trenches
104
.
Then, the photoresist pattern is removed. As shown in
FIG. 1B
, the entire surface of the substrate
100
where the trenches
104
were formed is subjected to a thermal oxidation process to form a first oxide film
106
on the surface of the substrate and along the inner wall of the trenches
104
. The formation of the first oxide film
106
is carried out for recovery of any substrate silicon components that may have been damaged by the STI dry etching process during formation of the trenches
104
.
Thereafter, the first oxide film is removed, as shown in FIG.
1
C. The reference numeral
110
denotes the final shape of the trenches resulting after removal of the first oxide film, in distinction from the reference numeral
104
.
Subsequently, as shown in
FIG. 1D
, a second oxide film
112
is formed by depositing an insulating film, such as a silicon oxide film or the like, on the resulting substrate, using a Chemical Vapor Deposition (CVD) process. The second oxide film is etched using a Chemical Mechanical Polishing (CMP) process or etch back process, so that a device isolation film is formed which is filled in the respective final trenches
110
with the second oxide film
112
.
FIG. 2
is a cross-sectional view showing drawbacks occurring by utilizing the method of the prior art shown above. In the method according to the prior art, shown in
FIGS. 1A-1D
, as the STI dry etching process for formation of the trenches is carried out, defects are caused at portions of the silicon substrate where the trenches were formed. If the substrate is subjected to a thermal oxidation process in a state where the defects are not removed, the oxidation rate at the bottom portion of the trenches is then significantly different from the oxidation rate at the sidewall portion thereof. In other words, the sidewall portion of the trench is far higher than the bottom portion in oxidation rate. For this reason, the linewidth between device isolation films will have a dimension far greater than 0.1 &mgr;m.
In addition, if the substrate including the trenches having the different oxidation rate is subjected to an ion implantation process, there is a problem in that the trenches act as a trap site of impurities.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method of semiconductor device isolation, which can finely define the design rule of active region between trenches to have a dimension less than 0.1 &mgr;m by maintaining the oxidation rate of the bottom portion of the trenches at the same level as that of the sidewall portion thereof.
To accomplish this object, there is provided a method of semiconductor device isolation, which comprises the steps of providing a substrate where a device isolation region was defined; removing the device isolation region of the substrate using a photolithography process to form trenches; implanting ions into the substrate having the trenches to form an impurity layer having a uniform depth relative to the surface of the substrate; oxidizing the substrate having the impurity layer to form an oxide film; and removing the oxide film.


REFERENCES:
patent: 5879986 (1999-03-01), Sung
patent: 5970352 (1999-10-01), Shiozawa et al.
patent: 5981326 (1999-11-01), Wanlass
patent: 6030882 (2000-02-01), Hong
patent: 6054344 (2000-04-01), Liang et al.
patent: 6069047 (2000-05-01), Wanlass
patent: 6090672 (2000-07-01), Wanlass
patent: 6096618 (2000-08-01), Dunn et al.
patent: 6103592 (2000-08-01), Levy et al.
patent: 6194285 (2001-02-01), Lin et al.
patent: 6214670 (2001-04-01), Shih et al.
patent: 6255152 (2001-07-01), Chen
patent: 2001/0055861 (2001-12-01), Patti et al.
patent: 2002/0155708 (2002-10-01), Lo et al.

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