Method of selectively forming local interconnects using...

Details Method of selectively forming local interconnects using... Method of selectively forming local interconnects using...

2000-08-31

2003-03-18

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C438S652000, C438S655000, C438S656000, C438S657000, C438S660000, C438S674000, C438S598000, C438S618000

Reexamination Certificate

active

06535413

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the fabrication of solid state devices and, more particularly, to the fabrication of local interconnects.
2. Description of the Background
Local interconnects are a mechanism used during the fabrication of solid state devices to make connections between structures, such as between the terminals of transistors, to thereby provide electrical interconnections between devices. “Local interconnects”, as the name implies, refers to interconnects that extend between adjacent devices, or devices that are relatively close to one another, as opposed to connections extending across a circuit or chip. Connections that are approximately thirty microns or less are typically referred to as local interconnects.
One type of circuit where local interconnects are used is a six transistor, static random access memory, or 6T SRAM. A circuit diagram of a 6T SRAM cell is illustrated in FIG.
9
. In
FIG. 9
, a 6T SRAM cell
10
is coupled between complimentary bit lines
12
and
14
and is coupled to a word line
16
. Memory cell
10
includes a load transistor
18
, a load transistor
20
, a drive or pull down transistor
22
and a drive or pull down transistor
24
. Transistors
18
,
20
,
22
and
24
are coupled together to form cross-coupled inverters having a storage node
26
and a storage node
28
.
Transistors
18
and
20
are preferably P-channel transistors, but may be replaced by polysilicon or other resistors, N-channel depletion mode transistors, or other electrical devices for raising the voltage at storage nodes
26
and
28
when pull down transistors
22
and
24
are turned off, respectively. Pull down transistors
22
and
24
are preferably N-channel transistors, although other types of transistors such as bipolar transistors or other devices may be utilized.
Storage node
26
is coupled to a pass gate transistor
30
which is controlled by word line
16
. Storage node
28
is coupled to a pass gate transistor
32
which is also controlled by word line
16
. Pass gate transistors
30
and
32
are preferably N-channel enhancement mode transistors, although other types of transistors may be utilized.
Transistors
18
and
22
form a first inverter having an input at conductive line
23
, and transistors
20
and
24
form a second inverter having an input at conductive line
25
. Conductive line
23
is coupled to the output of the second inverter formed by transistors
20
and
24
(i.e. storage node
28
). Similarly, conductive line
25
is coupled to the output of the first inverter formed by transistors
18
and
22
(i.e. storage node
26
). Thus, transistors
18
,
20
,
22
and
24
form cross coupled inverters having outputs at storage nodes
26
and
28
.
In operation, cell
10
stores logic signals, or information such as a logic 1 (e.g., VCC) or logic 0 (e.g., ground) on nodes
26
and
28
.
With reference to
FIG. 10
, a top view schematic layout drawing of a portion of cell
10
is shown. Transistors
18
,
20
,
22
and
24
are illustrated as lateral transistors. Alternatively, transistors
18
,
20
,
22
and
24
can be vertical transistors, or thin film transistors. A gate
34
of transistor
22
is coupled to node
28
via polysilicon conductive lines
23
and
36
and a gate
38
of transistor
24
is coupled to node
26
via polysilicon conductive lines
25
and
40
. Lines
23
,
36
and
25
,
40
cross couple transistors
18
,
20
,
22
and
24
.
A drain
42
of transistor
22
is coupled to node
26
via a local interconnect
44
, and a drain
46
of transistor
24
is coupled to node
28
via a local interconnect
48
. A source
50
of transistor
22
is coupled to ground, and a source
52
of transistor
24
is coupled to ground.
The local interconnect
44
is electrically coupled to the polysilicon conductive line
25
at node
26
. The local interconnect
48
is electrically coupled to the polysilicon line
23
at the node
28
. Local interconnects
44
and
48
can be any conductive material such as doped polysilicon, amorphous polysilicon, a single layer of metal (tungsten), or other substances. Additionally, local interconnects
44
and
48
can each be coupled to various other items associated with cell
10
or other integrated circuit elements. Preferably, local interconnects
44
and
48
are utilized to provide additional connections for cell
10
.
U.S. Pat. No. 5,831,899 entitled Local Interconnect Structure And Process For Six-Transistor SRAM Cell discloses a method of fabricating local interconnects and a local interconnect that is comprised of a glue layer and a plug layer. An etch is performed to remove the plug layer from above the surface of the insulating layer. That leaves the glue layer for forming the local interconnects.
The particular geometry, and materials described with reference to
FIG. 10
are shown only as exemplary embodiment. The particular geometry of cell
10
can be adjusted various ways to provide particular operating parameters for cell
10
. For example, transistors
18
,
20
,
22
and
24
can be provided at various orientations to form cell
10
. Changes in orientation will change the location of the local interconnects. Design rules are used to determine the size and position of structures within a given circuit design.
Some of the design rules which must be considered when designing a 6T SRAM cell utilizing local interconnects as well as other types of memory cells and other devices are explained with reference to FIG.
11
. In
FIG. 11
, a moat
58
underlies a conducting line
60
. These two elements are generally separated by a dielectric (not shown). A transistor may be formed from these elements. A conducting line
62
is located outside of moat
58
. Local interconnect
64
overlies and connects moat region
58
and conducting line
62
.
As is well known, design rules must be formulated and applied to any integrated circuit design configuration or process. These rules specify minimum (or maximum) distances for reliability and operation of the device. The rules are dependent upon many factors such as the variability in dimensions of the structures fabricated and the variability in alignment of one structural material to another. Both variabilities depend in turn on fabrication techniques applied and tolerances of the equipment used in fabrication. Illustrated in
FIG. 11
are five minimum design rules which together dictate the minimum width to which the configuration shown may be fabricated. Distance “a” is the minimum line width for a polysilicon conducting line for a given device and fabrication process. A minimum distance “a” may be, for example, 0.8 &mgr;m. Note that the distances specified herein for design rules are exemplary only and would vary for different configurations and design processes. Distance “b” is the distance required between two conducting lines. A typical minimum distance “b” may be 1.0 &mgr;m. Distance “c” represents the minimum allowed distance between a local interconnect and an unrelated conducting line. This distance may be, for example, 0.7 &mgr;m. Distance “d” is the distance that the local interconnect
64
overlaps the moat region
58
. A typical minimum design rule for distance “d” is 0.8 &mgr;m. Distance “e” is the distance that the local interconnect
64
overlaps the conducting line
62
. A typical design rule minimum for distance “e” may be 0.6 &mgr;m. As can be seen then, the minimum width for this configuration from one conducting line to the other, including the width of both lines, must be at least a+c+d+e+(a−e). For the exemplary design rule distances given above, that would result in a minimum distance of 3.1 &mgr;m.
Additionally, it can be seen that the alignment of the local interconnect
64
over the conducting line is critical to achieve minimum distance “e” while not extending over the conducting line to thereby increase the width. Thus, production of local interconnects requires the careful alignment of a dedicated local interconnect mask.

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