Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
1999-06-01
2001-07-24
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S374000
Reexamination Certificate
active
06265275
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of semiconductor devices, and, more particularly, to a transistor.
BACKGROUND OF THE INVENTION
The application titled “Low-Noise Vertical Bipolar Transistor and Corresponding Fabrication Process” discloses a method for producing a vertical bipolar transistor with a silicon/germanium heterojunction base and an epitaxial emitter on the upper surface of the base. During production of such a transistor, a region of the intrinsic collector lying under the emitter window is selectively doped to increase the speed of the transistor. In other words, the value of its transition frequency, i.e., cutoff frequency for the current gain, and the value of its maximum oscillation frequency, i.e., cutoff frequency for the power gain, are increased.
This selective doping is preferably carried out on two successive phosphorus implantations through the heterojunction base, which has been epitaxially grown beforehand on the surface of the intrinsic collector. For these implantations, use is made of the resin block which was used for etching the emitter window to obtain implantation of the overdosed zone of the collector, which is aligned with the emitter window.
However, implanting through the base creates defects in it which will cause diffusion of the boron in the base. The extent of this will become greater as the dopant dose implanted in the intrinsic collector increases. Lastly, implanting through the base leads to broadening of the base, which causes a reduction in the speed of the transistor. Furthermore, the defects actively contribute to relaxing the SiGe layer, which generates dislocations, thus short-circuiting the junctions of the transistor.
SUMMARY OF THE INVENTION
An object of the present invention is to increase the speed of vertical bipolar transistors.
A further object of the invention is to optimize the value of the collector resistance while avoiding an excessive increase in the collector/base capacitance.
A vertical bipolar transistor includes a silicon-germanium heterojunction base, and is intended to be integrated in high-frequency technologies with very large scale integration (VLSI). The intrinsic collector of such a transistor is selectively overdoped with silicon/germanium (SiGe)in the heterojunction epitaxial base.
A method for selectively doping the intrinsic collector of a vertical bipolar transistor with a silicon/germanium heterojunction includes the step of producing the intrinsic collector by epitaxy or implantation on an extrinsic collector layer buried in a semiconductor substrate. The method further includes the step of producing a side insulation region surrounding the upper part of the intrinsic collector and an offset extrinsic collector well. A silicon/germanium heterojunction base is produced lying above the intrinsic collector and the side insulation region including nonselective epitaxy of a stack of layers of silicon and silicon/germanium, e.g., a stack of one SiGe layer encapsulated by two silicon layers. A first implantation of dopants is provided in the intrinsic collector, which is carried out through a first implantation window before the nonselective epitaxy is formed above the intrinsic collector.
A second implantation of dopants in the intrinsic collector with a lower implantation dose and lower energy than the first implantation is performed through the epitaxially grown stack via a second implantation window lying inside the first window formed above the stack and self-aligned with the emitter. This self-alignment of the second implantation with the emitter, in particular, is produced by using the definition mask of the emitter window as the implantation mask for the second implantation. The second implantation window is then the same size as the emitter window.
In other words, a first implantation of dopants in the intrinsic collector is carried out before the formation of the stack within which the intrinsic base is produced. This implantation is high-energy implantation. A second implantation of dopants in the intrinsic collector is then carried out through the epitaxial base. This second implantation has an implantation dose lower than the implantation dose of the first, which is typically by a factor of 10. Therefore, this results in a much lower level of defects in the stack, which leads to obtaining a thinner intrinsic base and consequently an increase in the speed of the transistor.
Furthermore, making two separate implantations of dopants in the intrinsic collector makes it possible to adjust the width of the first implantation window independently of the width of the second implantation window. Although the two implantation windows could be chosen with the same size, it is particularly advantageous to choose a first implantation window which is wider than the second to be able to widen the first overdoped zone implanted in the collector, and thus to be able to reduce the collector resistance. In the case in which this first implantation window is widened, a person skilled in the art will thus be readily able to adjust the implantation dose and the implantation energy of this first implantation to avoid an excessive dopant rise in the silicon. Consequently, this avoids an excessive increase in the collector/base capacitance.
According to one approach of the method, in which the step of producing the base includes, before forming the epitaxial grown stack, the opening of a base window is formed over the intrinsic collector in a protection layer, e.g., amorphous silicon. This base window extends over the side insulation region. A specific implantation mask, whose first implantation window is wider than the second implantation window, but less wide than the base window, is used for the first implantation of dopants in the intrinsic collector.
As a variation, the mask for etching the base window may be used for the first implantation of the dopants. The first implantation window is then identical in size to the base window. This makes it possible to save on one mask and to obtain an overdoped lower zone of the collector extending over the entire width of the active zone, which leads to a yet further reduction in the collector resistance.
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Ren et al,Silicon Nitride as Dielectric in the Low Temperature SiGe HBT Processing, Jun. 1997, vol. 36 No. 1-4, p. 179-182, p. 180; figure 1.
Burghartz et al,An Ultra Low Thermal-Budget Sige-Base Bipolar Technology, May 17, 1993, Digest of Technical Papers of the Symposium on VLSI Technology, Kyoto p. 59/60, Institute of Electrical and Electronics Engineers figure 1.
Chantre Alain
Marty Michel
Schwartzmann Thierry
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nguyen Tuan H.
STMicroelectronics S.A.
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