Method of selectively alloying interconnect regions by ion...

Details Method of selectively alloying interconnect regions by ion... Method of selectively alloying interconnect regions by ion...

2001-06-20

2003-10-14

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S776000, C257S763000, C257S765000, C257S767000, C257S643000, C438S694000, C438S687000, C438S688000, C438S689000

Reexamination Certificate

active

06633085

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing, and more particularly, to reduction of electromigration voids in metal interconnect structures.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the submicron features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization. Conventional semiconductor devices typically comprise a semiconductor substrate, usually a doped monocrystalline silicon (Si), and plurality of sequentially formed interlayer dielectrics and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by inter-wiring spacings. Typically, the conductive patterns of vertically spaced metallization layers are electrically connected by vertically oriented conductive plugs filling via holes formed in the interlayer dielectric layer separating the metallization layers, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and micro-miniaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization layers is known as “damascene” -type processing. Generally, this processing involves forming an opening (or via) in the dielectric interlayer, which will subsequently separate the vertically spaced metallization layers. The via is typically formed using conventional lithographic and etching techniques. After the via is formed, the via is filled with conductive material, such as tungsten or copper, using conventional techniques. Excess conductive material on the surface of the dielectric interlayer is then typically removed by chemical mechanical planarization (CMP).
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Aluminum is conventionally employed because it is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, as the size for openings for vias/contacts and trenches is scaled down to the submicron ranges, step coverage problems result from the use of aluminum. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide material, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with aluminum, and these problems have decreased the reliability of interconnections formed between various metallization layers.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization layers. Copper and copper-based alloy metallization systems have very low resistivities, which are significantly lower that tungsten and even lower than those of previously preferred systems utilizing aluminum and its alloys. Additionally, copper has a higher resistance to electromigration. Furthermore, copper and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver and gold. Also, in contrast to aluminum and refractory-type metals, copper and its alloys can be readily deposited at low temperatures formed by well-known (wet) plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with requirements of manufacturing throughput.
FIG. 1
depicts a schematic cross-section of a portion of a metal interconnect structure employing copper damascene technology. The lower level metal layer
10
(including a copper line), also referred to as M
1
, is connected to a higher level metal layer
16
(including a copper line) through a via
14
. Barrier layers
18
and
20
, formed of nitride, for example, cover the metal layers
10
,
16
. The metal layer
10
,
16
are separated by a dielectric layer
12
, such as formed by an oxide, for example. The via
14
is filled with metal to form a conductive plug
15
.
The formation of the via
14
involves performing a via etch through the dielectric layer
12
and the barrier layer
20
, stopping on the underlying metal layer
10
. A pre-sputter etch process, using argon, for example, is normally employed prior to the via barrier and copper deposition.
Electromigration (EM) has been defined as the transport of metal atoms by momentum exchange between electrons, moving under the influence of a field, and metal ions. Two of the critical interfaces for electromigration in the copper damascene structure of
FIG. 1
are the interface V
1
M
1
at
22
and V
1
M
2
at
24
. Electromigration testing of the V
1
M
1
interface
22
involves flowing electrons from the upper copper line in metal layer
16
(M
2
) through the conductive plug
15
and the via
14
and into the lower copper line in metal layer
10
(M
1
). Electromigration testing of the V
1
M
2
interface
24
involves electrons flowing in the opposite direction. In the case of the V
1
M
1
interface
22
, electromigration voids typically generate at the copper
itride or (copper/barrier) interface at the via
14
. This is depicted in
FIG. 2
, where the electromigration void
26
is shown. The presence of a electromigration void
26
reduces the reliability of the device.
When aluminum is used as the interconnect material, it is well known that many alloy elements may be employed to improve the aluminum resistance to electromigration. One of the most widely used alloy elements is copper in aluminum. When copper is added in small concentrations to aluminum, the electromigration reliability increases by orders of magnitude. Similarly, alloy elements for copper have been under study. However, there are process differences between aluminum and copper that render the insertion of an alloy in the copper process flow a challenging proposition. For example, aluminum is a deposition, pattern and etch process, while copper is typically a damascene process with a physical vapor deposition (PVD) seed and electrochemical fill process.
Attempts have been made to introduce the alloy into the copper lines during electrochemical deposition, but many alloys of copper are not electrically active in aqueous solution. Another potential solution is to sputter the copper alloys during the PVD copper seed deposition, but there is a problem in that the alloy elements tend to sputter at a different rate than the copper matrix since different metals have different sputter yields. Another problem has been all

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