Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-08-09
2004-06-29
Niebling, John F. (Department: 2812)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C438S460000
Reexamination Certificate
active
06756796
ABSTRACT:
FIELD OF INVENTION
This invention relates a method of search and identifying a reference die on a semiconductor wafer for pick and place equipment such as a die bonder, tape and reel or die sorter.
BACKGROUND OF INVENTION
The assembly manufacturing sites receive wafers from the Wafer Fabs, segregate the individual chips from each wafer, encapsulate the chips, and perform final tests before shipping the devices to the customers. The die bonding process where only good chips from a wafer are picked up is conventionally done by an ink dot mechanism. The pick and place equipment steps through each die on a wafer to detect and skip the ink-reject chips and only mount onto the leadframe the un-inked, good chips. With the improvements in process, equipment, and systems, we now have the opportunity to totally eliminate the ink-based process with the use of wafer maps.
In an Assembly/Test (A/T) facility, wafer maps are normally received from offsite locations such as Wafer Fab or Probe sites. A wafer map originates from the Wafer Fab on a Tester or Wafer mapper equipment at the probe process. A wafer map is a set of information that is used by process equipment when handling a wafer at its workstation. The map data includes the coordinates of each die on a wafer, bin assignments for good dies and reject dies, wafer orientation or rotation, and the wafer identification that is used to associate the wafer map with the physical wafer.
The wafer map host system receives the map data, provides storage, and enables data download into the production equipment to support inkless processing of wafers to manufacture a semiconductor product. The wafer map host system transforms the lot's wafer map ASCII file into a suitable map file for the pick and place equipment to handle and prepares them for equipment download. In the manufacturing floor, as the wafer goes through the assembly process, a barcode is generated for the wafer identification (ID) or the flexframe ID and is attached to the wafer. When the wafer is ready to be processed at the pick and place equipment, the flexframe or wafer ID barcode is scanned and is used to request the wafer map from the wafer map host system. The pick and place equipment uses the downloaded wafer map to directly step into the good chips for pick-up.
In the manufacture of semiconductor devices, wafers are formed with an incomplete circular edge terminating in a flat edge. The wafers are patterned into multiple dies separated by streets or saw cut lines to separate the dies. Some of these dies are good dies, some are full pattern dies and some are not, some are mirror dies, there may be plug dies or an ink die.
FIG. 1
illustrates these dies and the wafer edge. One of the dies is a reference die. The reference die is an important die to a pick and place equipment such as a die bonder to start a pickup operation. In some cases it is the first lower right regular die on the first regular die row. The die to the right of the reference die on the first regular die row is a mirror die. In another embodiment the reference die is to the left of a group of mirror dies at the lower right of the wafer but may not be located on the first row of full dies. In other words the region or neighborhood around the reference die may not always be the same. The location of this die is important because once locating this die a wafer map can be used to aid the pick and place equipment to find the dies without the use of the ink system. The reference die is located at a pre-determined column and row coordinate.
After the wafer is placed on the pick and place equipment, this equipment looks for the reference die. In the existing equipment in one wafer system, the reference die is found as illustrated in
FIG. 2
by moving the wafer table down from the center of the wafer toward the flat until the monitor shows the mirror die along wafer flat row. It then moves up the column one die away from the mirror die and then moves to the right one regular die at a time till the mirror die is located. The system moves back one die to the left to find the reference die. This works well if the placement of the wafer on the pick and place equipment is perfectly aligned and if the reference die is in the first row. If however the wafer placement on the pick and place equipment is rotated, the wafer edges, partial pattern dies, plug dies and mirror dies are rotated and the alignment may not be sufficient to identify the reference die. This becomes increasingly more difficult as the size of the dies becomes smaller.
It is therefore desirable to provide an improved method of finding and identifying the reference die.
SUMMARY OF INVENTION
In accordance with one embodiment of the present invention the neighboring dies are used as to search and identify the reference die.
In accordance with another embodiment of the present invention the wafer table is rotated one die at a time one die at a time and a neighborhood matrix of information is stored and the matrix is used in the searching for the reference die.
REFERENCES:
patent: 6174788 (2001-01-01), Balamurugan
patent: 6216055 (2001-04-01), Balamurugan et al.
patent: 6492187 (2002-12-01), Farnworth et al.
patent: 6509750 (2003-01-01), Talbot et al.
Brady III W. James
Niebling John F.
Stevenson Andre' C.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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