Method of screening hot temperature erase rejects at room temper

Details Method of screening hot temperature erase rejects at room temper Method of screening hot temperature erase rejects at room temper

1996-05-24

1998-05-12

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36518519, G11C 1134

Patent

active

057516332

ABSTRACT:
In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.

REFERENCES:
patent: 5410511 (1995-04-01), Michiyama
patent: 5600595 (1997-02-01), Ogura
patent: 5608679 (1997-03-01), Mi
patent: 5621687 (1997-04-01), Doller

Affiliated with

Also associated with

Rating

Method of screening hot temperature erase rejects at room temper does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of screening hot temperature erase rejects at room temper, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of screening hot temperature erase rejects at room temper will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-989447