Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter – Counter chains with a radix or base other than the number...
Patent
1995-02-28
1996-06-11
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Starting, stopping, presetting or resetting the counter
Counter chains with a radix or base other than the number...
377 29, 377111, H03K 2138
Patent
active
055263925
ABSTRACT:
A method and circuit for selectively scaling a binary counter having N serially connected stages in which an output count from the counter is 2.sup.M times the number of clock signals that have been input to the counter. The first M stages of the counter are selectively held so that clock signals by-pass (or pass through) the first M stages without change. The M+1 stage receives each clock signal and is thereby caused to indicate that 2.sup.M clock signals have been received, when only one clock signal has, in fact, been received. The output of each stage is provided to a decoder array that provides the scaled count signal. The method and circuit find application in systems in which normal unscaled operation of the binary counter may be selectively replaced with high speed operation, such as during tests or during special operating modes. The circuit and method obviate the need for a separate high speed clock, or for adaptive circuitry in the decoder array.
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Harmon Joseph W.
Sferrazza Paul K.
Harris Corporation
Heyman John S.
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