Method of scaling table based cell library timing models in...

Details Method of scaling table based cell library timing models in... Method of scaling table based cell library timing models in...

1999-03-09

2004-06-15

Jones, Hugh (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

Reexamination Certificate

active

06751579

ABSTRACT:

BACKGROUND
The present invention concerns design and manufacturing of integrated circuits and pertains particularly to a method of scaling table based cell library timing models for process, temperature and power supply.
When designing an integrated circuit, it is generally desirable to simulate the functioning of logic circuitry within the integrated circuit. In order to accurately access the performance of the circuitry, it is desirable that the logic simulation of logic include an accurate assessment of timing delays through the circuitry, at least in the critical paths.
In general, timing delays through circuitry are caused by propagation delays through and between logic cells which comprise the circuitry. The actual amount of propagation delay through and between logic cells is generally dependent on various capacitances within and between the logic cells, as well as the current available to charge or discharge the capacitances.
When developing a timing model, it is important, therefore, to take into account the time delay introduced by charging and discharging the input capacitance of logic cells. This time delay is directly affected by the input current available to charge or discharge the input capacitance to the logic cell. This input current, in turn, is directly affected by the fan out of the output of the logic cell providing the input current.
Timing models for logic circuits are often stored in a cell library used to design the logic circuit. The timing model is used in event driven simulation and synthesis of circuits constructed from the elements of the library. The timing model generally describes the cell delay between each input pin and output pin transition. There is often a separate timing model for each cell in the library.
For submicron circuits, an accurate cell delay model generally depends upon the ramp (or transition time) of the input pin for each cell in the library. The ramp is the time it takes for the voltage of the node to pass between two pre-specified values. Generally, the model also describes the ramp of the output pin. The output ramp model depends upon the load on the output pin. In addition, for some cells, the output ramp model also depends upon the input ramp.
In a tabular cell delay model, the information is stored in a list of output load indices (Load
1
, Load
2
, Load
3
, Load
4
, . . . , Load
m
) and in a list of input ramp indices (IR
1
, IR
2
, IR
3
, IR
4
, . . . , IR
n
), and a two-dimensional “m” by “n” array of cell delay values. For each input ramp index and each load index, there is listed an output ramp and a cell delay. This is done, for example, in a separate table for each of the output ramp and the cell delay. Depending upon the implementation, the input ramp indices and the output load indices may or may not be shared by the table for the output ramp and the table for the cell delay. For cells where the output ramp does not depend upon the input ramp, the table for the output ramp is simplified so that for each load index there is listed an output ramp.
The particular values chosen for the indices may vary depending upon the cell used. Also, for a particular cell, the particular values chosen for the indices may vary depending upon the input pin/output pin combination that a particular table represents.
For each transition of every cell in a cell library, quantitative information about the delay and output ramp is for a fixed process, power supply, and temperature, (P, V, T).
For example, in a two dimensional array of delays, each entry is listed as Delay [j,k]. The numerical value of Delay [j, k] represents the value of the delay between input and output of the transition when the load on the output node is equal to Load
j
and the rise or fall time of the input node voltage is equal to IR
k
. In a two dimensional array of output ramps, each output ramp is listed as OR [j,k]. The numerical value of OR [j,k] represents the value of the output ramp of the transition when the load on the output node is equal to Load
j
and the rise or fall time of the input node voltage is equal to IR
k
.
For other values of output load and/or input ramp different from the values in the list of indices, the value of delay and output ramp can be approximated by interpolation of the table values (or extrapolation, if the input ramp and/or output load are outside the range of the indices).
Typically in the industry the values of delay and output ramp are determined by running SPICE simulations for each transition of every cell in the library and to obtain the values of delay and output ramp from the output of the SPICE simulations. The SPICE simulations are run at each pair of values for input ramp and output load in the list of indices. This process is known as characterization. A complete library characterization at a fixed P, V, T may involve on the order of several hundred thousand SPICE simulations.
It is necessary to have cell library timing models at a variety of P, V, T conditions; at minimum three sets of conditions (typical, best case, and worst case) are required. It is desirable, however, to obtain accurate cell library models at a variety of P, V, T conditions without multiplying the characterization effort by the number of sets of P, V, T conditions needed.
It is therefore desirable to do a complete library characterization at a baseline set of P, V, T conditions and to accurately extrapolate these results to other P, V, T conditions.
In one prior art model, the delay and output ramp are described as explicit parametric formulas of input ramp, output load, process, power supply, and temperature. P, V, T. Variations are described by evaluating the formulas at different values of P, V, T. See, R. W. Phelps,
Advanced Library Characterization for High Performance ASIC, Proceedings of the IEEE International Asic Conference,
1991, pp. P15-3.1 through P15-3.4. However, characterization of the model for a fixed set of P, V, T conditions required 21 SPICE simulations for each transition. Characterization of the P, V, and T variations required 630 SPICE simulations for each transition. Incorporating P, V, T variations was accomplished at a cost of a factor of 30 in characterization effort.
In another prior art model, the delay and output ramp were described as explicit parametric formulas of input ramp and output load. P, V, T variations are described by 13 independent scaling factors. Each of the parameters of the model is multiplied by a scaling factor which depends upon P, V, and T. The scaling factors are the same for all cells and transitions. See U.S. Pat. No. 5,559,715 issued to Michael N. Misheloff for Timing Model and Characterization System for Logic Simulation of Integrated Circuits Which Takes into Account Process, Temperature and Power Supply Variations. While this method was effective, it did not become an industry standard and there is currently no software support for the model.
In another prior art model, P, V, T variations are incorporated using four independent scaling factors. All values of Delay [j, k] for rising output are multiplied by a scaling factor. All values of Delay [j, k] for falling output are multiplied by a second scaling factor. All values of OR [j, k] for rising output are multiplied by a third scaling factor. All values of OR [j, k] for falling output are multiplied by a fourth scaling factor. Each of the scaling factors depends upon P, V, and T. The scaling factors do not depend upon the value of the input ramp and output load. See the
Synopsis Design Compiler User Manual
available on the internet at (www.Synopsys.com) and from Synopsis, Inc. having a business address of 700 E. Middlefield Road, Mountain View, Calif. 94043-4033. However, this approach does not give sufficiently accurate results for many applications.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a method is presented for generating a timing model for a logic cell. Output load indices (Load
1
, Load
2

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