Multiplex communications – Wide area network – Packet switching
Patent
1994-09-22
1997-08-19
Bowler, Alyssa H.
Multiplex communications
Wide area network
Packet switching
39520079, 39520082, 370390, 370392, G06F 15163, G06F 1314, H04H 112
Patent
active
056596863
ABSTRACT:
In a parallel processor, a plurality of data processing nodes are intercoupled through an array of message routing circuits. Each message routing circuit has multiple input channels on which messages are received and multiple output channels on which messages are sent. A message on an input channel of any one particular message routing circuit contains a header followed by data with the header consisting of a sequence of control characters which route the data. Depending on the control character sequence that is received on an input channel, the data is sent to one, two, or three output channels and each such data transmission is preceded by a respective modified header which is generated from the header on the input channel. By sequentially performing this message processing in a series of message routing circuits, the data is delivered to multiple nodes along a tree-shaped path.
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Bowler Alyssa H.
Fassbender Charles J.
Gregson Richard J.
Petersen Steven R.
Starr Mark T.
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