Method of rewriting in nonvolatile semiconductor memory device

Details Method of rewriting in nonvolatile semiconductor memory device Method of rewriting in nonvolatile semiconductor memory device

1998-09-10

2000-05-30

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518518, 36518514, 36518501, G11C 1604

Patent

active

060698268

ABSTRACT:
A P-type well 4 is set to an externally supplied ground potential. An N-type well 3 and a P-type well 5 are set to 3.3 V. A control gate electrode 14 is set to -6.5 V. A drain 10 is set to 6.5 V. A source 9 is set to 3.3 V or opened. Thus, a difference is 13 V between the control gate electrode 14 and the drain 10. A sufficient amount of tunnel current is generated between the drain 10 and a floating gate electrode 12. In this manner, the P-type well 5 is set to a positive voltage with respect to the externally supplied ground potential, whereby it is possible to reduce an absolute value of a negative voltage applied to the control gate electrode 14 and also to reduce a potential difference between the drain 10 and the P-type well 5. Thus, a memory transistor can be finely formed, have high reliability and have a low threshold voltage.

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IDEM 94-921, H. Kume et al, IEEE Technical Dig. of IEDM, pp. 992, 1992.

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