Electrical computers and digital processing systems: multicomput – Bused computer networking
Patent
1998-04-30
2000-06-06
Matar, Ahmad F.
Electrical computers and digital processing systems: multicomput
Bused computer networking
709219, 709225, 709243, 710200, 712217, 712219, G06F 1516, G06F 15173
Patent
active
060731826
ABSTRACT:
A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks may occur in such a system due to specific sequences of requests, either because high priority requests use priority cycles and lock out low priority requests, or because requests of any priority level make resources needed for the completion of other requests too busy. The mechanism logic monitors the length of time a request has been valid in the storage controller without completing, by checking the request register valid bits, and by utilizing a timed pulse which is a subset of the pulse used to detect hangs within the storage controller. If the valid bit is reset at any time detection logic and an internal hang detect latch is set, Logic which allows requests in progress to complete, and holds new requests in an inactive state is activated when the internal hang latch is set and remains active until the request which detected the internal hang is able to complete, thus resetting the internal hang detect latch.
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Blake Michael A.
Fee Michael
Jones Christine Comins
Mak Pak-kin
Strait Gary Eugene
Augspurger Lynn L.
Barot Bharat
International Business Machines - Corporation
Matar Ahmad F.
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