Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-02-29
2001-09-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S127000
Reexamination Certificate
active
06284565
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of resin-encapsulating a semiconductor chip and a mold-releasing film used in the method.
BACKGROUND OF THE INVENTION
In the package of semiconductor chips, the use of CSP (Chip Scale Package) has proceeded and a mold-releasing film is used in place of compounding a mold-releasing agent with a encapsulating resin to increase the mold-releasing property, whereby the improvement of the working efficiency by the reduction of a mold-cleaning frequency, the reduction of cost by prolonging the life of mold, etc., have been attempted. In this case, it is proposed to use a polytetrafluoroethylene film as the releasing film (JP-A-8-197567, JP-A-8-186141, etc.) (the term “JP-A” as used herein means an “unexamined published Japanese patent application”).
FIG. 1
shows QFN (Quad Flat Package) of the structure formed by removing the lower surface mold portion from QFP and cutting off the lead at the side from the mold side portion. In the case of carrying out resin encapsulating thereof, the electrode of a semiconductor chip
2
is bonded to the terminal
22
of each lead frame
21
with a wire, the semiconductor chip
2
is placed in the cavity
11
of a lower mold
1
with the terminals
22
being at the upper side as shown in FIG.
1
(A), the mold is closed by an upper mold
3
via a polytetrafluoroethylene film F and a resin is injected into the cavity by a transfer molding and is simultaneously cured as shown in FIG.
1
(B), the mold is then opened as shown in FIG.
1
(C), and the lead frames are trimmed leaving the terminals.
In the resin-encapsulating method, it is expected that the terminals bites into the polytetrafluoroethylene film by the mold closing pressure, whereby the terminals and the polytetrafluoroethylene film are always maintained at a contact state during resin encapsulating to exclude the occurrence of resin covering of the terminals.
As well known, the polytetrafluoroethylene film can be obtained by a casting method (a method of coating a dispersion of polytetrafluoroethylene on a carrier sheet followed by sintering and releasing the sintered film from the carrier sheet), a cutting method (a method of sintering a polytetrafluoroethylene rod and cutting the rod by a cutting lathe into a film), etc.
However, when the present inventors performed resin-encapsulating of semiconductor chips using the polytetrafluoroethylene film as the mold-releasing film, in spite of that there was no substantial difference in the modulus of elasticity and the exclusion of the occurrence of resin-covering of the terminal was similarly expected by cutting the terminals into the polytetrafluoroethylene film by mold-closing pressure to always maintain the terminals and the polytetrafluoroethylene film at a contact state during resin encapsulating, it has been found that the generation ratio of resin covering (inferiority ratio) of the above-described terminals considerably differs (practically, there is a difference of the inferiority ratio in the range of from 0 to 10/50) according to the difference in the above-described production method of the polytetrafluoroethylene film.
Accordingly, the inventors made the investigations on the cause thereof and have found that the cause is in the difference in the thermal shrinkage percentages between the lengthwise direction and the width direction of the mold-releasing film. That is, it is presumed that when a film has a directional property in the thermal shrinkage percentage, a force which shears and deforms the film slantingly is applied to the film to thereby cause creases.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of carrying out resin encapsulating of a semiconductor chip using the polytetrafluoroethylene film as the mold-releasing film, wherein resin encapsulating can be carried out at an excellent yield while preventing the occurrence of resin covering of the terminals or the top surfaces of electrodes.
That is, the first aspect of this invention is a method of resin-encapsulating a semiconductor chip by closing a lower mold having disposed in a cavity thereof a semiconductor chip equipped with terminals or post electrodes by an upper mold via a mold-releasing film made of a polytetrafluoroethylene film between the surface on which the terminals or the post electrodes are disposed and the upper mold and then injecting a resin into the cavity of the lower mold while curing, wherein a polytetrafluoroethylene film satisfies the conditions that the thermal shrinkage percentages in the longitudinal and width directions are 5% or lower, the difference between the thermal shrinkage percentages is within 3% and the ratio of the elastic modulus of the longitudinal direction to the elastic modulus of the width direction is from 0.5 to 2.0 during resin encapsulating.
The second aspect of this invention is a mold-releasing film used for a method of resin-encapsulating a semiconductor chip, wherein the mold-releasing film is made of a polytetrafluoroethylene film satisfying the conditions that the thermal shrinkage percentages in the longitudinal and width directions at 175° C. for 10 minutes are 5% or lower, the difference between the thermal shrinkage percentages is within 3%, and the ratio of the elastic modulus of the longitudinal direction to the elastic modulus of the width direction is from 0.5 to 2.0, and preferably from 0.8 to 1.5 during resin encapsulating. In the mold-releasing film made of the above-described polytetrafluoroethylene film, it is preferred that the breaking elongation percentages in the longitudinal direction and the width direction thereof at 175° C. are both at least 600% and further it is preferred that the surface roughness Ra (by a JIS B 0601 method) thereof is 0.3 &mgr;m or lower, and preferably 0.2 &mgr;m or lower.
REFERENCES:
patent: 4954308 (1990-09-01), Yabe et al.
patent: 5882692 (1999-03-01), Kojima et al.
patent: 5912320 (1999-06-01), Hotta et al.
patent: 5998243 (1999-12-01), Odashima et al.
patent: 6081978 (2000-07-01), Utsumi et al.
Iimura Mitsuo
Sato Kenji
Tachibana Toshimitsu
Dang Phuc T.
Nelms David
Nitto Denko Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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