Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-07-24
2003-09-09
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S125000, C438S455000, C438S612000
Reexamination Certificate
active
06617195
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to a method of using no-clean flux during the attaching of electronic components to substrates.
BACKGROUND OF THE INVENTION
Interconnection and packaging related issues are among the main factors that determine not only the number of circuits that can be integrated on an electronic computer chip (“chip”), but also the performance of the chip. These issues have gained in importance as advances in integrated circuit chip design have led to reduced feature sizes of transistors and enlarged chip dimensions. The semiconductor industry has come to realize that merely having a fast chip will not result in a fast system; it must also be supported by an equally fast and reliable package.
An increasingly important aspect of manufacturing an integrated circuit chip, also referred to as an integrated circuit die or semiconductor die, is the mounting of the die to a substrate to form a package. Essentially, the package, or packaging, supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Often times, the goal of this process is to provide the chip with as many input/output (“I/O”) terminals as possible. Another important function is simply to redistribute the tightly packed I/Os off the chip to the I/Os of a printed wiring board.
An example of a package-chip system is the “flip-chip” integrated circuit mounted on an area array organic package. Flip-chip mounting entails placing solder bumps on a die or chip, flipping the chip over, aligning the chip with the contact pads on a substrate, and re-flowing the solder balls in a furnace to establish bonding between the chip and the substrate. This method is advantageous in certain applications because the contact pads are distributed over the entire chip surface rather than being confined to the periphery as in wire bonding and most tape-automated bonding (TAB) techniques. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the chips.
In the flip-chip bonding process, the die is mounted directly to the substrate. A representation of a flip-chip
10
is illustrated in FIG.
1
. Generally, the flip-chip process entails forming regions of solder, e.g. solder bumps
12
, on contact pads on the circuit-bearing upper surface
14
of the die
16
. Such solder regions may also be formed on corresponding bonding pads
18
on the substrate
20
. Flux is then applied to the solder regions on the die
16
and/or to the corresponding bonding pads
18
and/or corresponding solder regions on the substrate
20
. Thereafter, the die
16
is flipped and the circuit-bearing upper surface
14
of the die
16
is brought to face the substrate
20
. The solder bumps
12
on the die
16
are then brought into contact with the corresponding bonding pads
18
. The resulting assembly of the die
16
and substrate
20
is then heated to melt and reflow the solder bumps
12
on the die
16
. Upon cooling and re-solidification, each solder bump
12
forms a solder connection between the die
16
and the substrate
20
, with the solder joint functioning as both an electrical and a physical connection. Also, the resulting solder joints between the die
16
and substrate
20
are typically encapsulated in an encapsulant
24
, also known as underfilling.
The solderjoints are made between solderable metallized surfaces, such as Cu,Cu plated with Pb-Sn, Ni, Ni plated with Au, and with lead solder or other solders containing Sb, Sn or Bi. Because the metallized surfaces to be bonded are typically heavily contaminated with metal oxides, carbon compounds, and other materials due to extended exposure in the manufacturing environment, the surfaces, therefore, require cleaning prior to bonding as a metallized surface contaminated by these materials is difficult to be wetted by solder. However, once this surface contamination is removed, the solder can wet the metallized surface and form a metallurgically sound solder joint.
Contaminants are typically removed from the metallized surfaces by the application of fluxes. A typical flux consists of active agents dissolved or dispensed in a liquid carrier, such as a flux paste. The carrier for flux is typically alcohol-based, with varying concentrations of acids or salts as activators. The function of the activators is to reduce base metal oxides. The flux has a variety of purposes, which include removing oxides from the metallization; removing oxides on the molten solder to reduce the surface tension and enhance flow; inhibiting subsequent oxidation of the clean metal surfaces during soldering; and assisting in the transfer of heat to the joint during soldering.
Many problems associated with the flip-chip process are generated by use of flux. Depending upon the type of flux, a flux residue remains after reflow welding during which the solder joint is formed. The residue can comprise a carrier, such as rosin or resin that is not evaporated, acid or salt deposits, and the removed oxides. If not removed, this residue can be detrimental to the long-term reliability of an electronic package. The resin can also absorb water and become an ionic conductor, which could result in problems such as electrical shorting, noise generation, and corrosion. Additionally, the residual activator can, over a period of time, corrode the soldered components and cause electrical opens.
The use of fluxes that leave corrosive and/or hygroscopic residues require a process to remove these residues to maintain the reliability of the electronic package. Typical post-soldering cleaning processes use chlorinated fluorocarbons (CFCs), organic solvents, semi-aqueous solutions, or water. However, many of these processes result in emission of CFCs and waste water, which detrimentally add to environmental pollution and production costs. In order to preserve the earth environment, the use of such CFCs has been regulated throughout the world. As an alternative to CFCs, non-regulated cleaning agents have been used. However, such cleaning agents are typically not sufficient to remove flux residue; and therefore, use of these cleaning agents cannot maintain the reliability of the electronic package.
In recent years, commercial interest in “no-clean” and low residue fluxes has significantly increased. The interest has moved from the simple desire to leave no visible residue to the unaided eye, to actually measuring the extent of ionic residue, even if it cannot be seen with the unaided eye. Initially, “no-clean” fluxes did not require post-soldering cleaning with environmentally unfriendly cleaners, as for example CFCs or chlorinated solvents, which rosin-based fluxes normally require. However, such no-clean fluxes can leave a residue that is visible. Thus, if any residue was left, it could be readily removed by rinsing with water or some other environmentally friendly solvent. Most recently, however, cleanliness requirements have increased, and a truly low residue flux, by current standards, leaves little or no measurable ionic or organic residue, even when no residue can be seen with the unaided eye.
Underfilling has been used to solve a problem in flip-chip mounting caused by a mismatch commonly found between the coefficient of thermal expansion of the semiconductor die and that of the substrate. Because of thermal gradients experienced by the semiconductor device during normal operation, the solder bumps which couple the die to the substrate experience significant stresses. These stresses can cause thermal fatigue and connection failures. Underfilling has been commonly used to overcome the thermal mismatch between the die and the substrate. This process involves inserting an encapsulation material, such as epoxy resin or other material, into the space between the semiconductor die and substrate after the die has been soldered to the substrate. In ad
Guardado Maria G.
Khan Mohammad Z.
Master Raj N.
Advanced Micro Devices , Inc.
Everhart Caridad
Luu Chuong A
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