Method of reducing waiting time jitter

Details Method of reducing waiting time jitter Method of reducing waiting time jitter

1991-05-09

1993-11-16

Kuntz, Curtis

Pulse or digital communications

Spread spectrum

Direct sequence

370102, H04L 7027

Patent

active

052630579

ABSTRACT:
A method of recovering an original digital signal, after pulse stuffing, with reduced waiting time jitter. The original digital signal is written into a first elastic memory in a synchronizer. A pulse stuffed output of the synchronizer is transmitted to a desynchronizer where bits of the original signal are written into second elastic memory. Average values of fill levels of elastic memories in a synchronizer and in a desynchronizer are determined. The average value determined in the synchronizer is transmitted to the desynchronizer where a comparison of the respective average values is made in a comparator. A clock signal generating circuit in a phase locked loop is controlled by an output signal of the comparator so as to generate a clock signal. The signal bits written into the second elastic memory are read out of the second elastic memory at the rate of the generated clock signal.

REFERENCES:
patent: 4095053 (1978-06-01), Duttweiler et al.
patent: 4731646 (1988-03-01), Kliem
patent: 4811340 (1989-03-01), McEachern et al.
patent: 4920547 (1990-04-01), Murakami
patent: 5067126 (1991-11-01), Moore

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