Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2004-08-26
2010-02-09
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S196000, C438S221000, C438S427000, C257SE21540, C257SE21628
Reexamination Certificate
active
07659180
ABSTRACT:
In one embodiment, a method of fabricating one or more transistors in an integrated circuit includes an annealing step prior to a gate oxidation step. The annealing step may comprise a rapid thermal annealing (RTA) step performed prior to a gate oxidation pre-clean step. Among other advantages, the annealing step reduces a step height difference between P-doped and N-doped regions of a field oxide of a shallow trench isolation structure. The shallow trench isolation structure may be separating a PMOS transistor and an NMOS transistor in the integrated circuit.
REFERENCES:
patent: 6124189 (2000-09-01), Watanabe et al.
patent: 6140191 (2000-10-01), Gardner et al.
patent: 6235568 (2001-05-01), Murthy et al.
patent: 6524901 (2003-02-01), Trivedi
patent: 6524904 (2003-02-01), Segawa et al.
patent: 6656764 (2003-12-01), Wang et al.
patent: 2002/0102775 (2002-08-01), Houng et al.
patent: 2004/0077171 (2004-04-01), Chuang et al.
S. Shishiguchi, et al., “The reduction of grain size in LPCVD poly-Si by in situ oxygen and phosphorus doping” 1996, pp. 689-693, Journal of Crystal Growth.
Kuang-Chao Chen, et al, “Applications of Single-Wafer Rapid-Thermal Processing to the Manufacture of Advanced Flash Memory” May 2003, pp. 128-137, IEEE Transactions on Semiconductor Manufacturing, vol. 16, No. 2.
Pierre C. Pazan, et al., “A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs” 1993, pp. 57-60, IEDM, IEEE.
Byung-Jin Cho, et al., “Evaluation of a vertical tube concept for RTP” 1993, pp. 165-169, Mat. Res. Soc. Symp. Proc. vol. 303, Materials Research Society.
Khoueir Antoine
Khoury Maroun
Zagrebelny Andrey
Cypress Semiconductor Corporation
Lee Cheung
Mulpuri Savitri
LandOfFree
Method of reducing step height difference between doped... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing step height difference between doped..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing step height difference between doped... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4215543