Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-31
2001-09-04
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S733000
Reexamination Certificate
active
06284666
ABSTRACT:
FIELD OF INVENTION
The present invention is related to the fabrication of semiconductor devices, and more particularly, to etching a high aspect ratio deep trench DRAM to build capacitors in Si substrates.
BACKGROUND OF THE INVENTION
The fabrication of deep trenches (DT) in Si substrates is one method of making charge storage cells, referred to as DT capacitors. A deep hole of somewhat conical shape is etched out of a Si substrate wafer by a commonly used dry etch method known as reactive ion etching (RIE). A dielectric material usually with a high dielectric constant is deposited in a form of a conformal layer inside a DT. The inner surface on one side of the trench, and a conductive or a semiconductor material fill on the other side of the dielectric material serve as capacitor plates. The film thickness of the dielectric material is inversely proportional to the charge the film can hold. Thus, the thickness of the film is kept to a minimum to the extent allowed by the process capability. The surface area of the dielectric film is directly proportional to the charge holding capacity, also known as capacitance. Accordingly, the capacitance of the device depends on the inner surface area of the DT etched in Si.
There is today an ever increasing need to make the DT smaller to conserve space on the substrate and, hence, to increase productivity. This reduction process is known to practitioners in the art as ground rule (GR) shrinking. The direct result of GR shrinkage is that the circumference or the perimeter of the DT ends up substantially reduced. In order to maintain the capacitance requirements of the DT capacitor, its depth must be constantly increased. Such a situation leads to a high aspect ratio, which is defined as the ratio of the depth of the etched structure relative to its width (i.e., if in a planar view, the structure is square or rectangular) or to its diameter (i.e., if in a planar view the structure is circular or elliptical in shape).
The etch process in general, and RIE process in particular, are heavily dependent on the aspect ratio of the structure. A typical RIE process used for etching generally involves the deposition of oxide (SiO
2
) or nitride (Si
3
N
4
) films used as a hard mask. A photolithography process is then employed to open holes in the hard mask. In subsequent steps, the holes are etched in the Si substrate to form the DT. The process of forming DT's using RIE is well known in the art, and is described, e.g., in U.S. Pat. No.4,784,720; 5,409,563; 5,501,893; 5,605,600 and 5,409,563.
The DT Si RIE process is relatively complex. Etching is performed in equipment wherein gaseous species, usually containing Cl
2
, F and Br, are ionized. Etching is achieved by a combination of several mechanisms such as ion bombardment, ion assisted chemical etching and chemical etching (dominated by radicals). The profile and shape control of DT is very important for other process reasons. The RIE process which is, essentially, a controlled way of deposition and etching are tailored to control the profile and prevent the isotropic etching. This objective is achieved by controlling the formation of deposition called passivation and its etching.
The role of passivation in DT etching and profile has been described by Muller et al. in the aforementioned U.S. Pat. No. 5,605,600, wherein the effect of substrate temperature on the formation of passivation is described in full detail. The process of high aspect ration etching is also described by Cathey in the previously mentioned U.S. Pat. No. 5,409,563.
With the requirement of GR shrinkage, the control of DT side wall (SW) passivation has become a fundamental issue and an impediment in achieving deeper DTs. As shown in
FIG. 1
, nitride (
20
) and oxide (
30
) films are conventionally deposited on a Si substrate
10
. The processes of lithography follows, and a hard mask consisting of films
20
and
30
is etched. After etching the hard mask, Si etching is performed and DT
40
is etched in the substrate. The process involves the formation of a passivation layer
50
. Known in the prior art is the fact that the process is designed in such a manner that the controlled growth of passivation layer
50
prevents isotropic etching to help control the DT profile. On average, the thickness of film
50
ranges from 20 to 40 nm in a conventional processes described in prior art. However, the presence of a thick passivation layer
50
on the entire inner surface of DT
40
during an etch process leads to a significantly slower Si etch rate. This event can be attributed to the aspect ratio which, typically, can exceed
45
. The aspect ratio dependent (ARD) slowdown of the Si etch rate is called RIE lag. One reason is that the thickness of film
50
continues to grow on each side of the DT
40
, leading to a further narrowing of the DT. The films
50
grow to the extent that they eventually join each other, blocking the passage of etch species into the DT and the removal of etch byproducts from the DT. This blockage is significant for smaller GR etch process in standard semiconductor manufacturing processes.
The aforementioned problem finds its way in many instances, e.g., during the construction of certain classes of semiconductor devices, such as DRAMs (dynamic random access memory) which typically use two types of capacitors to store charges: i) capacitors formed in deep trench holes in crystalline silicon and ii) stacked capacitors. The important device parameter in these memory devices is the capacitance value of the memory cell. Higher values are preferred to increase the charge retention time in these cells. In the case of trench capacitor based devices, the capacitance value of a cell is proportional to the trench wall area, which in turn depends linearly upon the trench depth for a given trench opening dimension. As previously described, achieving large trench depths is therefore of utmost importance to fabricating robust memory cells having large retention time.
The etching of trenches is normally performed in a complex plasma consisting of several gas mixtures. Silicon etching in these plasmas is by the reaction of neutral species, such as F, Br or other halogens, enhanced by ion activation of the silicon surface. High etch rates are achievable only if adequate neutral and ion flux as well as high ion energies are available at the etching front. Etching deep or high aspect ratio trench holes is therefore plagued by physical laws: the flux of neutral and ionic species at the bottom surface of the trench decreases with increase in depth or aspect ratio (AR) and the ion energy decreases at larger depths due to inelastic scattering of ions on trench walls. The reduction of etch rate results render the etching of deep trenches very difficult. This effect is generally called RIE lag or aspect ratio dependent etching (ARDE). Reduction of the RIE lag is important for achieving deep trenches with high etch rates.
The second factor in trench etching is anisotropy of the etched profiles. Because of close placement of trenches in a silicon chip of high memory density, it is necessary for the trench profiles to be near-vertical to prevent the merging of adjacent trench walls. Since some halogen species (e.g., F) in the plasma tend to etch silicon with high degree of isotropy, some type of sidewall passivation is needed to prevent lateral etching of silicon, particularly when F-containing gases (e.g., NF
3
, SF
6
) are used. The control of this passivation film becomes more critical if high AR trenches are to be achieved. In some processes in the literature, deposition of side wall passivation film is done by adding gases like oxygen to the etching plasma.
OBJECTS OF THE INVENTION
Accordingly, it is a primary object of the invention to provide a method of eliminating or at least minimizing RIE lag during the manufacture of DTs in DRAM devices or similar memory structures having a large aspect ratio (i.e., >30:1).
It is another object of the invention to provide an etching process that prevents the formation of a side wall
Kim Byeong Yeol
Kudelka Stephan P.
Lee Brian S.
Lee Heon
Mathad Gangadhara S.
Chen Kin-Chan
International Business Machines - Corporation
Schnurmann H. Daniel
Utech Benjamin L.
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