Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-08-10
2003-06-17
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
Reexamination Certificate
active
06580639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to the general field of fabrication of integrated circuits and, more particularly to the fabrication of short-channel FET devices for use in NAND type flash memory and techniques for reducing program disturb conditions disrupting the performance of such devices.
2. Description of Related Art
NAND type semiconductor nonvolatile memories offer several advantages over NOR type memories as described in the work of Arase (U.S. Pat. No. 5,812,457). One advantage of NAND type flash memories is the relatively low current requirements for programming such memories in comparison with NOR memories. On-chip boosting circuits are proposed by Arase as a mode for NAND programming. The work of Runaldue describes an on-chip self-boosting circuit for programming NAND gates (U.S. Pat. No. 5,160,860). However, as the dimensions of FET devices become ever smaller, it becomes increasingly difficult to fabricate reliable NAND type flash memories with self-boost.
FET devices typically have n-doped source and drain regions formed on a lightly p-doped silicon substrate forming the channel between the source and drain regions. At the junction of the source and channel, a region depleted of charge carriers forms. A second depletion region forms at the channel-drain junction. If the length of the channel is large compared to the width of the depletion regions, they do not interact and the FET behaves in a manner similar to isolated n-p junctions. However, for many applications, channel lengths become very small and may be less than 0.3 microns in modern integrated circuits. Such short channel lengths may cause the depletion regions to interact and otherwise lead to a class of “short channel effects” as described in standard reference works (for example, “Silicon Processing for the VLSI ERA: Volume 2, Process Integration” by S. Wolf, Lattice Press, 1990, pp. 338-347). Under the appropriate conditions, the depletion regions may overlap leading to the condition known as “punchthrough” and disruption in the functioning of the FET device. One method to limit the extent of the depletion regions is to limit the depth of the source/drain implants. However, limiting the lateral extent and depth of the source and drain as initially implanted on the substrate is only partially effective as species are prone to diffuse during later thermal processing.
Source/drain spreading by diffusion may be reduced by pre-amorphizing the substrate region into which source/drain implants are to be placed. That is, diffusion through amorphous silicon is significantly hindered in comparison with diffusion through polycrystalline silicon, as used by Lee (U.S. Pat. No. 5,266,510) and Talwar et. al. (U.S. Pat. No. 5,908,307). Thus, shallow implants to form source/drain regions preceded by amorphization of the substrate is one method of reducing the width of the depletion regions and avoiding punchthrough in short channel FETs.
A common method of ameliorating short channel effects, including punchthrough, is to increase the doping of the channel region, as increased channel doping leads to narrower depletion regions. Therefore, higher channel doping permits the use of shorter channel lengths before punchthrough occurs. However, a higher level of channel doping affects both the self-boosting voltage as well as the width of the depletion region. In order to be definite, we provide a numerical example.
FIG. 1
illustrates a segment of NAND type flash memory. The following numerical values are by way of illustration and not limitation. Applying 19 volts (for example) to word line (“WL”)
9
causes 19 volts to appear at both devices labeled
1
. For purposes of illustration we assume that this is sufficient for devices,
1
, to be programmed, as desired. The problem is to program only the desired devices,
1
, but not device
2
that we assume for this example is not to be programmed. The NAND flash memory depicted in
FIG. 1
uses self-boosting voltage to avoid programming device
2
. Applying 3.3 volts to bit line (“BL”) n−1 causes a self-boost voltage V
sb
, of (say) 6 volts to occur at circuit node
3
. Device
2
receives the difference between the word line voltage and the bit line voltage or, in this example, 13 volts. 13 volts is presumed to be insufficient to program device
2
leading to the desired and correct programming of this word in NAND memory.
However, increasing channel doping decreases self-boosting voltage. Thus, for devices having increased channel doping, V
sb
appearing at
3
may be only 2 volts, resulting in 17 volts being applied to device
2
. In many practical circumstances, a NAND memory designed to be programmed with 19 volts may also be programmed with 17 volts. Thus, device
2
will be erroneously programmed along with devices
1
resulting in incorrect data stored in word
9
. This “program disturb” is an undesirable side effect of increasing the channel doping to reduce punchthrough.
BRIEF SUMMARY OF THE INVENTION
The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to source/drain implanting. Typical ion bombardments would be by ions of silicon or germanium at energies of approximately 30 KeV delivering a dose of approximately 10
15
ions/cm
2
. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages, avoiding program disturbs, and maintaining proper FET function even when short channel lengths are employed.
REFERENCES:
patent: 5568421 (1996-10-01), Aritome
patent: 5874329 (1999-02-01), Neary et al.
patent: 6028788 (2000-02-01), Choi et al.
Chang Kent Kuohua
He Yue-Song
Huang Allen U.
Advanced Micro Devices , Inc.
Hoang Huan
Skjerven Morrill & MacPherson LLP
Wolken, Jr. George
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