Method of reducing mechanical stress on a semiconductor die...

Details Method of reducing mechanical stress on a semiconductor die... Method of reducing mechanical stress on a semiconductor die...

2006-04-28

2008-10-14

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S111000, C438S612000, C438S613000, C438S614000, C257S676000, C257S787000, C257SE23145, C257SE23145

Reexamination Certificate

active

07435624

ABSTRACT:
A method of reducing mechanical stress on an integrated circuit is disclosed including applying solder columns to the substrate for adding structural support to the package during the fabrication process.

REFERENCES:
patent: 5744383 (1998-04-01), Fritz
patent: 6731011 (2004-05-01), Verma et al.
patent: 6858470 (2005-02-01), Han et al.
patent: 2002/0079577 (2002-06-01), Ho
patent: 2004/0089717 (2004-05-01), Harari et al.
patent: 2005/0087846 (2005-04-01), Han et al.
patent: 2006/0125113 (2006-06-01), Liu et al.
patent: 2007/0020912 (2007-01-01), Nishiyama et al.
patent: 2007/0252254 (2007-11-01), Chiu
patent: 60012746 (1985-01-01), None
patent: 2005074337 (2005-08-01), None
International Search Report dated Oct. 18, 2007, International Application No. PCT/US2007/009944.

Affiliated with

Also associated with

Rating

Method of reducing mechanical stress on a semiconductor die... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing mechanical stress on a semiconductor die..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing mechanical stress on a semiconductor die... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4013835