Method of reducing loading variation during etch processing

Details Method of reducing loading variation during etch processing Method of reducing loading variation during etch processing

1997-06-30

1999-05-04

Picardat, Kevin M.

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

438599, 438926, H01L 2182

Patent

active

058997067

ABSTRACT:
In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.

REFERENCES:
patent: 4941031 (1990-07-01), Kumagai et al.
patent: 5132237 (1992-07-01), Matthews
patent: 5262354 (1993-11-01), Cote et al.
patent: 5278105 (1994-01-01), Eden et al.
patent: 5770884 (1998-06-01), Pogge et al.

Affiliated with

Also associated with

Rating

Method of reducing loading variation during etch processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing loading variation during etch processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing loading variation during etch processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1865112