Method of reducing ionic contamination in integrated circuit fab

Details Method of reducing ionic contamination in integrated circuit fab Method of reducing ionic contamination in integrated circuit fab

1993-11-09

1995-05-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437190, 437941, H01L 21306

Patent

active

054181739

ABSTRACT:
A method of fabricating integrated circuits is disclosed. A layer of doped silicon dioxide is deposited over a partially fabricated integrated circuit. The doped silicon dioxide is heated to permit it to attract sodium ions. After the doped silicon dioxide has been heated, it is removed by an etching process which exhibits great selectivity to the remaining underlying portion of the integrated circuit.

REFERENCES:
patent: 3632438 (1972-01-01), Carlson et al.
patent: 4590664 (1986-05-01), Prentice et al.
patent: 4980301 (1990-12-01), Harrus et al.
patent: 4988405 (1991-01-01), Martin et al.
patent: 5022958 (1991-06-01), Favreau
Kern, Werner; The Evolution of Silicon Waft Cleaning Technology, J. Electro-Chem. Soc. vol. 137, No. 6 Jun. 1990.

Affiliated with

Also associated with

Rating

Method of reducing ionic contamination in integrated circuit fab does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing ionic contamination in integrated circuit fab, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing ionic contamination in integrated circuit fab will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2140155