Method of reducing film stress on overlay mark

Details Method of reducing film stress on overlay mark Method of reducing film stress on overlay mark

2008-01-29

2008-01-29

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S462000, C438S975000

Reexamination Certificate

active

07323393

ABSTRACT:
An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

REFERENCES:
patent: 5640053 (1997-06-01), Caldwell
patent: 6288454 (2001-09-01), Allman et al.
patent: 6383910 (2002-05-01), Okada et al.
patent: 6596604 (2003-07-01), Lojek et al.
patent: 6774452 (2004-08-01), Ramkumar et al.
patent: 6801313 (2004-10-01), Yokota
patent: 6809420 (2004-10-01), Wong
patent: 6858441 (2005-02-01), Nuetzel et al.
patent: 6979526 (2005-12-01), Ning
patent: 2002/0016059 (2002-02-01), Okada et al.
patent: 2002/0081501 (2002-06-01), Hasegawa et al.
patent: 2003/0036021 (2003-02-01), Khan et al.
patent: 2005/0195398 (2005-09-01), Adel et al.

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