Method of reducing emitter dip in transistors utilizing specific

Details Method of reducing emitter dip in transistors utilizing specific Method of reducing emitter dip in transistors utilizing specific

1978-05-30

1980-10-07

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29578, 148187, 148190, 357 34, 357 63, 357 88, 357 90, H01L 21225, H01L 2936

Patent

active

042266505

ABSTRACT:
A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.

REFERENCES:
patent: 3493443 (1970-02-01), Cohen
patent: 3507715 (1970-04-01), Kaiser
patent: 3635772 (1972-01-01), Pestle et al.
patent: 3649387 (1972-04-01), Frentz et al.
patent: 3707410 (1972-12-01), Tauchi et al.
patent: 3717507 (1973-02-01), Abe
patent: 3748198 (1973-07-01), Basi et al.
patent: 3783050 (1974-01-01), Nanba et al.
patent: 3834953 (1974-09-01), Nakamura et al.
patent: 3852127 (1974-12-01), Lamming
patent: 3915767 (1975-10-01), Welliver
Fair et al., "Effect of Complex . . . Arsenic in Silicon", J. Appl. Physics, vol. 44, No. 1, Jan. 1973, pp. 273-279.
Fair, R. B., "Quantitative Theory . . . Arsenic Emitters", Ibid., vol. 44, No. 1, Jan. 1973, pp. 283-291.
Saraswat et al., "A New Bipolar Process--Borsenic", IEEE J. Solid-State Circuits, vol. SC-11, No. 4, Aug. 1976, pp. 495-500.
Gereth et al., "Localized Enhanced Diffusion in NPN Silicon Structures", J. Electrochem. Soc., vol. 112, No. 3, Mar. 1965, pp. 323-329.
Edel et al., "Stress Relief by Counterdoping", I.B.M. Tech. Discl. Bull., vol. 13, No. 3, Aug. 1970, p. 632.
Edel, W. A., "Stacking Fault Free Epitaxial Layers", Ibid, vol. 14, No. 5, Oct. 1971, p. 1654.
Ashar et al., "Transistor Fabrication", Ibid, vol. 14, No. 5, Oct. 1971, p. 1643.

Affiliated with

Also associated with

Rating

Method of reducing emitter dip in transistors utilizing specific does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of reducing emitter dip in transistors utilizing specific, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing emitter dip in transistors utilizing specific will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-617138