Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With non-planar semiconductor surface
Reexamination Certificate
2002-02-26
2004-04-06
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With non-planar semiconductor surface
C257S750000, C257S758000, C257S762000, C438S643000, C438S652000, C438S677000, C438S687000
Reexamination Certificate
active
06717236
ABSTRACT:
FIELD OF THE INVETION
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing electromigration in copper interconnect lines by doping their surfaces with a barrier material using wet chemical methods.
BACKGROUND ART
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-&mgr;m to 0.25-&mgr;m) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractory metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.
However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.
1
These problems have instigated further research into the formulation of barrier materials for preventing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices particularly having aluminum copper alloy interconnect lines, the industry has been investigating the use of various barrier materials such as titanium-tungsten (TiW) and tanium nitride (TN) layers as well as refractory metals such as titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), and their silicides.
2
Although the foregoing materials are adequate for Al interconnects and Al—Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. Further, though CVD and PECVD have been conventionally used for depositing secondary metal(s) on a primary metal interconnect surface, neither technique provides a cost-effective method of forming a copper-zinc alloy on a Cu interconnect surface. Therefore, a need exists for a low cost and high throughput method of reducing electromigration in a dual-inlaid copper interconnect line by filling a via with a copper-zinc (Cu—Zn) alloy electroplated on a copper (Cu) surface from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance.
DISCLOSURE OF INVENTION
Accordingly, the present invention provides a method of reducing electromigration in a dual-inlaid copper interconnect line by filling a via with a Cu-rich (e.g., approximately 99.8 at.% to approximately 98 at.%/o) copper-zinc (Cu—Zn) alloy electroplated on a copper (Cu) surface from a stable chemical solution, and by controlling the Zn-doping thereof (e.g., approximately 0.2 at.% to approximately 2.0 at.%), which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The present method involves filling the via by electroplating the Cu surface, such as a blanket Cu seed layer and a partial thickness plated Cu layer, in a unique nontoxic aqueous chemical electroplating solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants, thereby forming an electroplated Cu—Zn alloy fill having some degree of oxygen (O) concentration, wherein the Zn-doping is controllable by varying the electroplating conditions; and annealing the Cu—Zn alloy fill formed on the Cu surface in an environment such as vacuum, nitrogen (N
2
), hydrogen (H
2
), forming (N
2
H
2
), or mixtures thereof for reducing the O-concentration in the alloy fill, for modifying the grain structure of the Cu—Zn alloy fill as well as of the underlying Cu surface, and for forming a mixed Cu—Zn/Cu interface, thereby forming the dual-inlaid interconnect structure. The present invention further provides a particular electroplating method which controls the parameters of Zn concentration, pH, temperature, and time in order to form a uniform reduced-oxygen copper-zinc (Cu—Zn) alloy fill on a cathode-wafer surface such as a copper (Cu) surface for reducing electromigration in the device by deceasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.
More specifically, the present invention provides a method of fabricating a semiconductor device, having a reduced-oxygen copper-zinc (Cu—Zn) alloy fill formed on a copper (Cu) surface by electroplating the Cu surface in a chemical solution, generally comprising the steps of: providing a semiconductor substrate having a Cu surface (e.g., seed layer), the Cu surface having been formed by CVD, PVD, PECVD, ALD, or electroplating, an optional barrier layer, and an optional underlayer formed in a via; providing a chemical solution; immersing the Cu surface in the chemical solution, thereby forming a Cu—Zn alloy fill on the Cu surface in the via; rinsing the Cu—Zn alloy fill in a solvent; drying the Cu—Zn alloy fill under a gaseous flow; annealing the Cu—Zn alloy fill formed on the Cu surface, thereby forming a reduced-oxygen Cu—Zn alloy fill; planarizing the reduced-oxygen Cu—Zn alloy fill, the Cu surface, the optional barrier layer, and the optional underlayer, thereby forming a Cu—Zn alloy dual-inlaid interconnect structure; and completing formation of the semiconductor device.
By electroplating this Cu—Zn alloy fill in the via and on the cathode-wafer surface, such as a Cu surface, using a stable chemical solution in the prescribed concentration ranges and subsequently annealing the Cu—Zn alloy fill electroplated on the Cu surface, the present invention improves Cu interconnect reliability, enhances electromigration resistance, improves corrosion resistance, and reduces manufacturing costs. In particular, the present invention chemical solution is advantageous in that it facilitates formation of an acceptable Cu—Zn alloy fill over a wide range of bath compositions while the subsequent annealing step removes undesirable oxygen impurities from the formed alloy fill. The desirable Zn concentration in the Cu—Zn alloy fill, preferably in a range of approximately 0.2 at% to approximately 2.0 at% determined by X-Ray Photoelectron Spectroscopy (XPS) or Auger Electron Spectroscopy (AES), is controllable by varying the electroplating conditions and/or the bath composition. By so controlling the Zn-doping, the present method balances high electromigration performance against low resistively requirements. Additionally, the Cu surface (e.g., seed layer), being formed by a technique such as electroless deposition, ion metal plasma (IMT), self-ionized plasma (SIP), hollow cathode magnetron (HCM), chemical vapor deposition (CVD), and atomic layer deposition (ALD), is enhanced by the Cu—Zn alloy fill layer and is prevented from etching by the high pH value (i.e., basic) of the chemical solution from which the alloy fill layer is formed.
Further advantages arise from the present invention's superior fill-characteristics. The present Cu—Zn electroplating solution facilitates better filling of the via on an interconnect, especially for feature sizes in a dimensional range of approximately 0.2 &mgr;m to approximately 0.05 &mgr;m, thereby lowering the resistance of the formed Cu—Zn alloy fill (e.g., in a resistance range of approximately 2.2 &mgr;&OHgr;·cm to approximately 2.5 &mgr;&OHgr;·cm for approximately 1 at.% Zn content in a Cu—Zn alloy fill, as deposited). Further, the filli
King Paul L.
Lopatin Sergey
Nickel Alexander H.
Advanced Micro Devices , Inc.
Coleman W. David
Farjami & Farjami LLP
Lee Hsien Ming
LandOfFree
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