Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-10-16
2002-05-07
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S633000, C438S687000, C438S688000, C438S742000, C438S754000
Reexamination Certificate
active
06383935
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to chemical mechanical polishing and avoidance of dishing problems.
BACKGROUND OF THE INVENTION
Chemical mechanical polishing (CMP) is widely used as a method for planarizing surfaces since the advancing etch front associated with CMP tends to be independent of both the topography and compositional variations within the surface being treated. However, since the pad used for the CMP is soft, it has a slight tendency to follow concavities with the result that, over time, dishing occurs over soft or open areas.
Referring now to
FIG. 1
, we see there a substrate
11
whose upper surface includes a number of trenches or via holes such as
13
. A temporary depression
12
has been formed and partially filled with metal layer
14
. Sufficient metal was used to overfill the vias so that the surface
15
of the metal layer was about 2 microns above the floor of
12
.
FIG. 2
shows the same structure after conventional CMP according to the practices of the prior art. As intended, the thickness of the metal layer
14
has been reduced above all surfaces outside the trench. However, in addition, the metal surface
25
inside the trench has not been left entirely untouched, as was intended. Instead, some dishing has occurred together with some chemical erosion of the metal.
The present invention discloses a solution to this problem that prevents dishing and erosion without affecting the main process.
A routine search of the prior art was performed. The following references of interest were found: In U.S. Pat. No. 5,618,381, Doan et al. show a CMP process that uses a protective layer that polishes significantly more slowly than the metal being planarized. This causes material in the crests to be removed faster than material in the valleys, thereby enhancing planarization. Cheung, in U.S. Pat. No. 6,056,864, shows an ECD copper planarization process where the copper is wet etched or electrolytically etched and the subjected to CMP. In U.S. Pat. No. 5,885,900, Schwartz shows a global planarization process for conductive layers using a wet etch back step while Joshi et al. (U.S. Pat. No. 5,731,254) show using a CuGe hard cap during CMP.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for chemical mechanical polishing of a surface that includes a dense trench array filled with metal.
Another object has been that said process lead to little or no dishing of the trenches.
A further object has been that said process lead to little or no erosion of the metal in the trenches or of the surrounding oxide.
These processes have been achieved by first covering the trenches with a material whose polishing rate under CMP is similar to that of the metal in the trenches. Spin-coating is used so that only the depression in which the trenches lie gets filled. After CMP, any residue of this material is removed leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.
REFERENCES:
patent: 5618381 (1997-04-01), Doan et al.
patent: 5683924 (1997-11-01), Chan et al.
patent: 5731245 (1998-03-01), Joshi et al.
patent: 5885900 (1999-03-01), Schwartz
patent: 6056864 (2000-05-01), Cheung
patent: 2000-3491 (2000-08-01), None
Chang Weng
Lin Cheng Chung
Shih Tsu
Yu Chen Hua
Ackerman Stephen B.
Nguyen Ha Tran
Saile George O.
Taiwan Semiconductor Manufacturing Company
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