Method of reducing dice testing with on-chip identification

Details Method of reducing dice testing with on-chip identification Method of reducing dice testing with on-chip identification

1993-06-10

1994-11-01

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

148DIG162, 365201, H01L 2166, G01R 3126

Patent

active

053607473

ABSTRACT:
A method is provided which includes on-chip identification of individual die. The first wafer sort includes the steps of programming a plurality of dice on a wafer, programming predetermined memory memory cells on each good die to identify the wafer on which that die is located, and storing the location of each good die in a file created for each wafer. Then, the plurality of dice are subjected to predetermined conditions. In the second wafer sort, predetermined memory cells on one die are accessed to determine the associated file of that die. The associated file is then loaded. Finally, the good dice are tested. In another embodiment, the first wafer sort includes identifying the first good die on the wafer. After the next good die on the wafer is found, that die is programmed to indicate the location of the proceeding good die. This programming step is repeated until the last good die on the wafer is programmed. Once again, the wafer is subjected to adverse conditions. During the second wafer sort, the last good die on the wafer is identified and tested. Then, the next die location indicated by the tested die is tested. These steps of indicating the next die and testing that die are repeated until the first good die is tested. The present invention significantly reduces valuable test time by an amount directly related to the initial yield. Moreover, the present invention reduces wear and tear on the test equipment itself, thereby increasing the longevity of this expensive piece of equipment.

REFERENCES:
patent: 4703436 (1987-10-01), Varshney
patent: 5256578 (1993-10-01), Corley et al.

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