Method of reducing delays

Details Method of reducing delays Method of reducing delays

2005-06-28

2005-06-28

Paladini, Albert W. (Department: 2125)

Data processing: structural design, modeling, simulation, and em

Electrical analog simulator

Of electrical device or system

C703S014000, C703S019000

Reexamination Certificate

active

06912494

ABSTRACT:
A method is described for reducing delays in an analogue simulation model of a hardware circuit. The method includes the steps of stimulating via an input an output of said analog model, said output and said input having a relatively high resistance therebetween and applying a pulse to a relatively low resistance, whereby when said pulse is applied to the relatively low resistance, the input is connected to said output via the relatively low resistance so that the time constant of the circuit is reduced.

REFERENCES:
patent: 4791593 (1988-12-01), Hennion
patent: 4815024 (1989-03-01), Lewis
patent: 6090152 (2000-07-01), Hayes et al.
patent: 6219822 (2001-04-01), Gristede et al.

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