Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
1999-10-25
2001-08-21
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S634000, C438S689000, C438S735000, C438S737000, C438S740000
Reexamination Certificate
active
06277716
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method for etching a polysilicon gate and gate oxide stack that reduces gate oxide damage by using a multi-step etch process using a special end point detection (e.g., nitrided) Silicon layer to create an early endpoint trace.
2) Description of the Prior Art
Plasma etch processes and apparatus are generally well known for etching materials for semiconductor device fabrication. The process begins with an application of a masking material, such as photoresist, to a silicon wafer. The masking pattern protects an area of the wafer from the etch process. The wafer is then placed in a plasma reactor (i.e., etcher) and etched. Subsequent steps are determined by the type of device being fabricated.
A common silicon etch process is based on fluorine. When mixtures such as CF
4
&O
2
are dissociated in an electrical discharge, fluorine atoms are liberated and volatilize the silicon as SiF
4
. Nevertheless, these processes are isotropic, i.e., they etch in all directions at the same rate. Moreover, anisotropic or vertical etches in silicon are not observed when fluorine is the sole etchant.
For vertical (anisotropic) etches of silicon, the use of gas mixtures, such as C
2
F
6
& Cl
2
, is known. The C
2
F
6
serves as a source of “recombinants”, such as C
3
. The recombinants suppress lateral etching (in the horizontal direction) by recombining with Cl atoms which have been adsorbed on the etched polysilicon sidewalls. Etching can proceed in the vertical direction (perpendicular to the wafer surface) because ion bombardment from the plasma suppresses the recombination mechanism.
Further, the selectivity of etchant between polysilicon and an underlying gate oxide (poly:oxide selectivity) must be as high as possible to minimize oxide loss.
Conventionally, instrumental analysis methods such as mass spectrometry and spectroscopic analysis are used to detect the end point of etching processes. The spectroscopic analysis is relatively simple and highly sensitive. With spectroscopic analysis, a specific active species is selected from radicals, ions, decomposed and reacted products of the etching gas Light strengths of the emission spectrum of this selected active species are measured. The active species selected depends upon the kind of etching gas. When etching gas of the fluorocarbon series such as CF
4
is used to etch silicon oxide film, the spectrum (specifically wavelengths 219 nm, 483.5 nm or others) emitted from the reacted product CO* is measured. When the fluorocarbon series etching gas such as CF
4
is used to etch silicon nitride film, the spectrum (specifically wavelengths 674 nm or others) emitted from the reacted product N* is measured. The end point of an etching process is decided by comparing changing values, which represents the light strength of the above-mentioned active species having a specific wavelength and primary and secondary differential ones of these light strength values, with a threshold value previously set.
In addition to an etch step, most conventional processes include an overetch step. Overetching is necessary in order to ensure that no residues are left on the wafer. If etching was stopped at the “end point”, as determined by optical emission from the plasma, only parts of the wafer would be completely etched while other parts would still be covered with remaining polysilicon. This is due to non-uniformity of both the initial polysilicon film thickness and the etch rate. Moreover, most of the current polysilicon dry processes use an overetch gas.
Recent advances have required that the gate oxide thickness be below 30 Å, forcing the endpoint process to improve selectivity to ensure that there is no damage to the gate oxide and substrate surface. The inventor's current methodology to overcome this is to have a timed etch for about 80% of the polysilicon (stack) thickness. Then change to a more selective etch chemistry to endpoint. The disadvantages of this are that if there are variations in the stack (e.g.,. polysilicon) thickness or in the characteristics of the etch machine drift, the % poly stack etch would vary thus making the triggering of endpoint unstable and unrepeatable.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 4,447,290(Matthews), U.S. Pat. No. 5,188,980(Lai), U.S. Pat. No. 5,789,294(Choi) and U.S. Pat. No. 5,453,156(Cher et al.) show gate stack etch processes.
U.S. Pat. No. 5,747,380(Yu et al.), U.S. Pat. No. 5,739,051(Saito), and U.S. Pat. No. 5,500,076(Jerbic) show etch processes with endpoint detecting.
However, an improved process/gate stack structure is needed to reduce etch damage to the thinner gate dielectric layers.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an etch method and polysilicon gate stack structure that allow for an accurate stack etch and minimal damage to the gate oxide layer.
It is an object of the present invention to provide a multi-step etch method and polysilicon gate stack structure having a special endpoint detect layer that allow for an accurate stack etch and minimal damage to the gate oxide layer.
It is an object of the present invention to provide a multi-step etch method and polysilicon gate stack structure where the stack is used as a dopant stop layer.
To accomplish the above objectives, the present invention provides a method of fabricating a gate stack having a special endpoint detection layer that emits an endpoint detection signal before the polysilicon is etched down to the underlying gate dielectric. The invention also has a multi-step etch process which has higher selectivity etch steps as the etch proceeds down to near the gate dielectric layer to prevent damage to the gate dielectric layer. Also, the endpoint detect layer can be used as a dopant stop layer to prevent dopants from diffusing from the gate stack to the gate dielectric.
The invention begins by forming a gate dielectric layer over a substrate. We then form an endpoint detect layer over the gate dielectric layer. A gate stack is formed over the bottom silicon layer. Then a mask is formed over the gate stack. The mask defines a gate electrode.
We etch the gate stack and the endpoint detect layer using multi-step etch comprising preferably 3 steps. In a main etch step, the gate stack and the endpoint detect layer are etched using a first etch chemistry. Upon an endpoint detection signal generated by etching the gate stack, the first etch step is stopped.
In an endpoint etch step, using a second etch chemistry, we etch the gate stack layer and the endpoint detect layer stopping the endpoint etch step when an endpoint detect signal changes upon reaching the gate dielectric layer. The second etch chemistry having a higher selectivity from the gate dielectric layer to the gate stack layer and endpoint detect layer than the first etch chemistry.
In an overetch step, using a third etch chemistry, we etch the endpoint detect layer without damaging the gate dielectric layer.
The invention's special endpoint detect layer emits an endpoint signal that allows the etch chemistry to be changed to a more selective polysilicon (or gate stack) to oxide (gate dielectric) ratio to prevent damage to the gate oxide layer.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4447290 (1984-05-01), Matthews
patent: 51
Chhagan Vijaikumar
Pradeep Yelehanka R.
Tjoa Tjin Tjin
Ackerman Stephen B.
Chartered Semiconductor Manufacturing Ltd.
Le Vu A.
Owens Beth E.
Pike Rosemary L. S.
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