Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
1999-04-20
2001-09-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S760000, C438S457000, C438S977000, C438S959000
Reexamination Certificate
active
06284628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of recycling a silicon wafer by reprocessing a delaminated (split) wafer produced as a by-product in a hydrogen ion delaminating method (also called a smart cut method) wherein an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is delaminated to thereby obtain an SOI (silicon on insulator) wafer. Particularly, the present invention relates to a method of reprocessing the delaminated wafer many times, and reusing it many times.
2. Description of the Related Art
Conventionally, two methods have gained wide notice as methods of fabricating wafers having an SOI structure. One method is a SIMOX (separation by implanted oxygen) method in which oxygen ions are implanted into a silicon monocrystal at a high concentration, and heat treatment is then performed at a high temperature in order to form an oxide layer. The other method is a bonding method in which two mirror-polished silicon wafers are bonded together without use of adhesive, and one of the wafers is subsequently made very thin.
In the SIMOX method, the thickness of an SOI layer that becomes a device active region can be determined and controlled through adjustment of an acceleration voltage at the time of oxygen ion implantation. Therefore, the SIMOX method has an advantage of enabling easy formation of a thin SOI layer having a high uniformity of thickness. However, the SIMOX method has many problems in relation to the reliability of a buried oxide layer, the crystallinity of the SOI layer, necessity of heat treatment at a temperature of 1300° C. or higher, and the like.
Meanwhile, in the wafer bonding method, an oxide film is formed on at least one of two mirror-polished silicon single crystal wafers, which are bonded together without use of adhesive and then subjected to heat treatment (typically, at 1100-1200° C.) in order to strengthen the bonding; subsequently, one of the wafers is subjected to grinding or wet etching such that the wafer becomes a thin film, the surface of which is then mirror-polished to form an SO layer. Therefore, the reliability of the buried oxide layer is high, and the crystallinity of the SOI layer is good.
However, since the thin film is formed by means of mechanical machining, it takes long time to form the thin film, and a great portion of one of the wafers is pulverized to be lost. Therefore, productivity is extremely low, and production cost is significantly high. Furthermore, there are limits to the thickness and thickness uniformity of the resultant SOI layer in formation of the thin film by grinding and polishing by means of mechanical machining.
Furthermore, most of waters used in the wafer bonding method are CZ wafers produced by Czochralski method (CZ method). However, it has been found in recent years that there exist in the CZ wafer crystal defects called COP (Crystal Originated Particle) which are incorporated while the crystal is growing. Accordingly, when the CZ wafer is used as a bond wafer which is to be a device active layer, COP exists also in the SOI layer, and pierces through the SOI layer which is very thin as required recently to form a pin hole which extremely degrades electric characteristics of the wafer.
To solve the problem, there is proposed, for example, a method wherein CZ wafer on which an epitaxial layer is grown is bonded to other wafer on the side of the epitaxial layer, and the silicon wafer which constitutes a base is ground and polished to form a SOI layer (see Japanese Patent Application Laid-open (Kokai) No.7-254689). According to the method, the above mentioned crystal defects such as COP can be surely eliminated. However, since it is necessary to use an expensive epitaxial wafer, production cost of the SOI wafer gets far higher.
When FZ wafer is used, there is no problem in relation to defects due to oxygen or the above mentioned COP, since no oxygen is contained in the FZ wafer. However, since only one SOI wafer can be obtained from two silicon wafers, there still exists the problem of high production cost.
In the wafer bonding method, not only silicon wafers are bonded together, but also a silicon wafer may be bonded directly to an insulator wafer of SiO
2
, SiC, Al
2
O
3
or the like, in order to form an SOI layer.
Recently, public attention has been drawn to a new method of fabricating an SOI wafer in which an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is delaminated (split) to thereby obtain an SOI wafer (hydrogen ion delaminating method: so-called smart-cut method). In this method, an oxide film is formed on the surface of at least one of two silicon wafers; and hydrogen ions or rare gas ions are implanted into the surface of one of the two silicon wafers in order to form a fine bubble layer (enclosed layer) within the wafer; the ion-implanted silicon wafer is superposed on the other silicon wafer such that the ion-implanted surface comes into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to delaminate a portion of the ion-implanted wafer while the fine bubble layer is used as a delaminating plane, in order to form a thin film; and heat treatment (bonding heat treatment) is further performed to firmly bond the thin film and the other wafer, to thereby obtain an SOI wafer (see Japanese Patent Application Laid-Open (kokai) No. 5-211128 or U.S. Pat. No. 5,374,564). Also, in this method, since the surface formed as a result of delamination is a good mirror-like surface, an SOI wafer whose SOI layer has a high thickness uniformity is obtained with relative ease.
Also in the hydrogen ion delaminating method described above, not only silicon wafers are bonded together, but also an ion-implanted silicon wafer may be bonded directly to an insulator wafer of SiO
2
, SiC, Al
2
O
3
, etc., in order to form an SOI layer.
When the SOI wafer is fabricated by the hydrogen ion delaminating method, a silicon delaminated wafer is inevitably produced as a by-product. It has been proposed to reuse such a delaminated wafer as a by-product so that one SOI wafer can be obtained substantially from one silicon wafer, and thereby to reduce production cost significantly.
It is conceptually possible to reuse the delaminated wafer, but there has been no actual cases of reusing the delaminated wafer, and the specific means for reusing it has not yet been known. The inventors of the present invention have studied and found that the wafer as just delaminated cannot be reused for the following reasons: a step is present in the peripheral part of the wafer; a damage layer due to ion implantation is present on the surface thereof; and surface roughness thereof is large. Accordingly, it is necessary to remove the step in the peripheral part of the wafer, the damage layer, or the like, in order to reuse the delaminated wafer as a silicon wafer.
In this case, it may be conceived that the surface of the delaminated wafer is ground, and then polished in order to remove the step in the peripheral part and the damage layer, and to improve surface roughness or the like. However, in order to improve the surface properties by grinding and polishing, long processing time and a lot of stock removal are required. Moreover, in the case that an epitaxial layer is used as a bond wafer in the hydrogen ion delimitation method, and SOI layer is made of an epitaxial layer, since the epitaxial layer remaining on the delaminated layer is completely removed, the epitaxial layer cannot be reused as a SOI layer. Accordingly, cost for fabrication of SOI wafer cannot be reduced.
In the case that CZ wafer is used as a bond wafer, the problems in relation to the above-mentioned COP cannot be solved by grinding and polishing. In the case that FZ wafer is used as a bond wafer, a lot of stock removal in grinding or polishing means the small number of times of reuse, and further, long processing time, and high production cost.
SUMMARY OF THE INVENTION
The present invention has
Aga Hiroji
Kuwahara Susumu
Mitani Kiyoshi
Wada Masae
Hogan & Hartson LLP
Niebling John F.
Shin-Etsu Handotai & Co., Ltd.
Simkovic Viktor
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