Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Reexamination Certificate
2008-05-06
2008-05-06
Jeanglaude, Jean B (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
C341S100000, C341S101000
Reexamination Certificate
active
11374929
ABSTRACT:
Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop. The second phase interpolator is controlled with a pointer monitor that monitors the write and read select pointers in the FIFO buffer to adjust the timing of the read clock signal relative to the write clock signal. With this method, the hunting jitter is filtered out while a frequency offset is still allowed between the reference clock and the data signal.
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Goller Joerg
Priego Antonio
Brady III Wade J.
Franz Warren L.
Jeanglaude Jean B
Telecky , Jr. Frederick J.
Texas Instruments Deutschland GmbH
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