Method of reading an NVM cell that utilizes a gated diode

Details Method of reading an NVM cell that utilizes a gated diode Method of reading an NVM cell that utilizes a gated diode

2011-07-12

2011-07-12

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210, C365S185270

Reexamination Certificate

active

07978519

ABSTRACT:
A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time.

REFERENCES:
patent: 5940324 (1999-08-01), Chi et al.
patent: 6160739 (2000-12-01), Wong
patent: 2009/0279360 (2009-11-01), Lee et al.
patent: 2009/0310414 (2009-12-01), Lee et al.

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