Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-08
2003-11-18
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185200
Reexamination Certificate
active
06650568
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a read operation technique for reading data held in a nonvolatile semiconductor memory.
2. Description of the Related Art
Nonvolatile semiconductor memories such as a flash memory store data by having electrons injected into the insulators of their memory cells for changes in threshold voltage. The memory cells rise in threshold voltage when their insulators contain electrons, and fall when the insulators contain no electron. When the memory cells of a flash memory are to store binary data, a state of high threshold voltage where no current flows through the memory cells in read operations is the state where “data 0” is written (“0 state”). A state of low threshold voltage where currents flow through the memory cells in read operations is the state where “data 1” is written (“1 state”).
The “0 state” and the “1 state” are detected by comparing the currents flowing through the memory cells in read operations (memory cell current) with a reference current.
Nonvolatile semiconductor memories of this type are ever growing in memory capacity (memory density) year by year. As a technique for increasing the memory density, level multiplication has been proposed of memory cells. To store multileveled data into each single memory cell, however, the amount of electrons to be injected into the memory cell must be precisely adjusted to secure read margins. In general, it is difficult to adjust the amount of injection of electrons precisely. In the case of storing multileveled data into memory cells by using this technique, small variations in the semiconductor processes can easily cause a drop in yield. Moreover, to store multileveled data into the memory cells, a plurality of reference currents are required for the sake of detecting the logical values of the data. In the meantime, techniques in which the integration level of memory cells is raised by raising the integration level of word lines to heighten storage density have been disclosed in Japanese Unexamined Patent Application Publication No. Hei 2-231772 and so on.
FIG. 1
shows the cell structure of a memory cell array in a nonvolatile semiconductor memory disclosed in this kind of publication.
This nonvolatile semiconductor memory is characterized in that second word lines WL
2
having a wiring width different from that of first word lines WL
1
are arranged in between these first word lines WL
1
. The first and second word lines WL
1
and WL
2
, lying over memory cells, function as control gates. Formed under the control gates are floating gates which are shown shaded in the diagram. The floating gates are formed on a silicon substrate via an oxide film, in between bit lines BL which are made of a diffusion layer.
In the diagram, the sources S and drains D of cell transistors (hereinafter, referred to as first memory cells) are formed at the intersections of the first word lines WL
1
and the bit lines BL. Then, the channel regions CH of the first memory cells are formed between the sources S and the drains D. Similarly, the sources S and drains D of cell transistors (hereinafter, referred to as second memory cells) are formed at the intersections of the second word lines WL
2
and the bit lines BL. The channel regions CH of the second memory cells are formed between the sources S and the drains D.
In this nonvolatile semiconductor memory, after the first word lines WL
1
and the floating gates corresponding to these word lines WL
1
are formed, the second word lines WL
2
and the floating gates corresponding to these second word lines WL
2
are formed in the gaps between the first word lines WL
1
. On that account, the gate width W
2
of the second memory cells MC
2
becomes smaller than the gate width W
1
of the first memory cells MCI. As for the channel lengths (the intervals between the sources S and drains D), the first memory cells MC
1
and the second memory cells MC
2
are identical to each other.
FIG. 2
shows an equivalent circuit of the memory cell array shown in FIG.
1
.
A plurality of first memory cells MC
1
are connected in series along the first word lines WL
1
. The sources S and drains S (data input/output nodes) of adjoining memory cells MC
1
are connected to respective common bit lines BL. A plurality of second memory cells MC
2
are connected in series along the second word lines WL
2
. The sources S and drains D (data input/output nodes) of adjoining memory cells MC
2
are connected to common bit lines BL This kind of memory cell array is generally referred to as a memory cell array of virtual ground type.
FIG. 3
shows an overview of the read operations of data retained in the memory cells of the nonvolatile semiconductor memory described above.
To read data from a first memory cell MC
1
, the first word line connected to this memory cell MC
1
is supplied with a read voltage of, e.g., 2.5 V. The bit lines BL connected to the source and drain of the first memory cell are supplied with 0 V and 5 V. When the first memory cell MC
1
is in the “0 state”, the memory cell turns off due to its high threshold voltage, so that no memory cell current flows between the bit lines BL. When the first memory cell MC
1
is in the “1 state”, the memory cell turns on due to its low threshold voltage, so that a memory cell current flows between the bit lines BL.
Similarly, to read data from a second memory cell MC
2
, a read voltage of 2.5 V is supplied to a second word line WL
2
, and 0V and 5V are supplied to bit lines BL on both sides of the second memory cell MC
2
. When the second memory cell MC
2
is in the “0 state”, no memory cell current flows. When the second memory cell MC
2
is in the “1 state”, a memory cell current flows. Then, the memory cell current is compared with a reference current IREF to detect whether the “0 state” or the “1 state” the memory cell MC
1
(or MC
2
) retains.
Nevertheless, as described above, the gate width WI of the first memory cells MC
1
is different from the gate width W
2
of the second memory cells MC
2
. The values of the memory cell currents at the turning-on of the cell transistors of the memory cells MC
1
and MC
2
depend on the ratios W/L between the gate widths W and channel lengths L of the cell transistors. Accordingly, in “1 state” read, the memory cell current of the second memory cells MC
2
become smaller than that of the first memory cells MC
1
.
The reference current IREF needs to be set at between the maximum value and the minimum value of the memory cell currents. This requires that the reference current IREF be set in accordance with the second memory cells MC
2
which have a smaller memory cell current in the “1 state”. As a result, in the first memory cells MC
1
, the “0 state” read margin M
0
becomes smaller than the “1 state” read margin M
1
with a problem of lower reliability.
Conventionally, there has not been proposed any reliable technique for reading data retained in the memory cells of a nonvolatile semiconductor memory that has a plurality of word lines of different wiring widths (gate widths).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a nonvolatile semiconductor memory having a plurality of word lines of different-wiring widths in which data retained in the memory cells is read with reliability.
It is another object of the present invention to provide a nonvolatile semiconductor memory of virtual ground type in which data retained in the memory cells is read with reliability.
According to one of the aspects of the present invention, memory cell currents flowing through memory cells during data readout are compared with reference currents that are set in accordance with the wiring widths of word lines connected to the memory cells. Then, depending on whether larger or smaller the memory cell currents are than the reference currents, the logic levels of data retained in the memory cells are detected. The word lines also function as control gates of the cell transistors of the memory cells. That is, the wiring widths of the word
Fujitsu Limited
Hoang Huan
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