Method of quickly evaluating contact resistance of semiconductor

Details Method of quickly evaluating contact resistance of semiconductor Method of quickly evaluating contact resistance of semiconductor

1994-06-28

1995-09-12

Wieder, Kenneth A.

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

324719, 324 731, G01R 2708, G01R 3126

Patent

active

054500168

ABSTRACT:
A large number of evaluating cells are arranged in a semiconductor chip, and each of the evaluating cells is implemented by first, second and third impurity regions, a first gate electrode formed over a channel between the first and second impurity regions and a second gate electrode formed over a channel between the first and third impurity regions, wherein current is sequentially supplied to the evaluating cells so that current flows from the first impurity region to the second impurity region; however, no current flows through the third impurity region, and a potential difference between the first and third impurity regions is reported as a contact resistance at the first impurity region.

REFERENCES:
patent: 4628144 (1986-12-01), Burger
patent: 4672314 (1987-06-01), Kokkas
patent: 4896108 (1990-01-01), Lynch et al.
patent: 5239270 (1993-08-01), Desbiens
patent: 5293133 (1994-03-01), Birkner et al.

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