Method of providing power to an integrated circuit

Details Method of providing power to an integrated circuit Method of providing power to an integrated circuit

1991-06-21

1992-12-22

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

29827, 174 524, H05K 334

Patent

active

051724715

ABSTRACT:
A CMOS integrated circuit assembly for providing reduced power supply and ground inductances has a first conducting layer which is formed over an insulating layer formed on top of the integrated-circuit chip. The first conducting layer is connected to wire bond pads which are wirebonded to a package. This first conducting layer forms a single, low-inductance conductor for a VDD supply voltage and extends over a substantial area so that it has an inductance significantly less than the inductance of a conventional conductor. A second conducting layer is forms a low-inductance VSS conductor. Power can be selectively distributed through conductive layers of this to provide power supply isolation between selected circuits of the integrated circuit.

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Reduced Ground Bounce and Improved Latch-Up Suppression Through Substrate Conduction by T. Gabara, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1224, 1232, Oct. 1988.

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