Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2000-12-21
2003-04-01
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S386000, C438S389000, C438S561000
Reexamination Certificate
active
06541347
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of improving planarity of a photoresist. More particularly, the present invention relates to forming a lower electrode of a trench capacitor by executing the method of improving planarity of the photoresist, therefore, the process yield of the forming of the trench capacitor is easily controlled.
2. Description of the Prior Art
DRAM is memory capable of reading and writing information. Each DRAM cell needs only one transistor and one capacitor, therefore, it is easy to reach higher integration to make it broadly applicable to computers and electric equipment. A trench capacitor is one of the most used capacitors, which is formed in the semiconductor silicon substrate. With the enhancement of the depth of the trench capacitor in the semiconductor silicon substrate, the surface area of the trench capacitor is increased, so that the capacitance is increased. The chip with trench capacitors can be separated into a memory cell array area used to store data and a decoupling capacitor area used to filter noise.
The traditional fabricating method of the trench capacitors is described below. Many trenches are formed in a semiconductor silicon substrate. An As-doped silicon oxide layer is covered over with the semiconductor silicon substrate with trenches. The silicon oxide layer is patterned with lower electrode patterns by coating and baking a photoresist. The photoresist can flow into the trenches in the baking step. Then the hardened photoresist, after baking, is removed by dry etching until the upper surface of the photoresist is lower than that of the semiconductor silicon substrate by a predetermined distance. The exposed silicon oxide layer is removed by using the photoresist as a mask. Then, the doped ions, As, in the silicon oxide layer is drived into the semiconductor silicon substrate to form a conducing layer as a lower electrode of the trench capacitor.
The capacitance of the trench capacitor is related to the surface area of the lower electrode, which is determined by the area of the silicon oxide layer covering the trench. The area of the silicon oxide layer covering the trench is controlled by the distance between the upper surface of the photoresist and that of the semiconductor silicon substrate. However, the distance is hardly controlled. Because the adhesion between the photoresist and the silicon oxide layer is too weak to make the photoresist flow into the trench after spin coating. During the baking of the photoresist, the photoresist can flow into the trenches. Nevertheless, the densities of the trenches in the memory cell array area and in the decoupling capacitor area are different. A mass of the photoresist flows into the trenches in the higher density area (the memory cell array area) so that the surface of the hardened photoresist is lower. A small quantity of the photoresist flows into the trenches in the lower density area (the decoupling capacitor area) so that the surface of the hardened resist is higher. Therefore, there is a height difference existing in the surface of the hardened resist in different areas.
Moreover, the difference of the distances between the upper surface of the photoresist and that of the semiconductor silicon substrate in different trenches exists after wet etching the photoresist. For example, under the design rule of 0.175 &mgr;m, the above-mentioned difference reaches 1.2 &mgr;m. If in order to prevent the lower electrode in the lower density area (the decoupling capacitor area) and the buried strap (or called ion doped band) subsequently formed in the top of the semiconductor silicon substrate from short, the lower electrode formed in the memory cell array area has a smaller surface area, which will damage the storage performance. If in order to enhance the surface area of the lower electrode in the memory cell array area, the breakdown voltage between the lower electrode in the decoupling capacitor area and the buried strap will be reduced, and may even short the circuit. Therefore, there is difficulty in etching the photoresist. It is also possible that whole process fails.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a method of improving planarity of a photoresist.
Furthermore, the present invention provides a method to effectively control the distance between the upper surface of the substrate and the upper surface of the photoresist under different kinds of densities that exist in trenches.
Moreover, the present invention provides a manufacturing method of trench capacitors, so as to prevent the capacitors in the decoupling capacitor area from invalidation, and prevent the capacitances in the memory cell array area from reducing.
Also, the present invention provides a manufacturing method for trench capacitors, which can increase the breakdown voltage between the lower electrode and the ion doped band to enhance the reliability of the capacitors.
The present invention provides a method of improving planarity of a photoresist, comprising: providing a silicon oxide layer having a plurality of trenches therein; modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and a photoresist; coating the photoresist over the silicon oxide layer, wherein the photoresist flows into the trenches of the silicon oxide layer; and performing a baking process.
The present invention provides a manufacturing method of a lower electrode of a trench transistor, comprising: providing a substrate having a plurality of trenches therein; forming a conformal silicon oxide layer over the substrate, wherein the silicon oxide layer is doped with a conducting dopant; modifying a surface of the silicon oxide layer to enhance the adhesion between the silicon oxide layer and a photoresist; coating the photoresist over the substrate, wherein the photoresist flows into the trenches of the substrate; removing a part of the photoresist till a distance exists between the upper surface of the photoresist and the upper surface of the substrate; removing the exposed silicon oxide layer; removing the photoresist; and driving the conducting dopant into the substrate to form a lower electrode.
In accordance with the present invention, the method of modifying the surface of the silicon oxide layer comprises performing an oxygen plasma treatment, or performing a wet treatment with a mixed solution of H
2
SO
4
and H
2
O
2
, or performing a wet treatment with a mixed solution of NH
4
OH and H
2
O
2
.
REFERENCES:
patent: 4529621 (1985-07-01), Ballard
patent: 4994409 (1991-02-01), Yoon et al.
patent: 5817550 (1998-10-01), Carey et al.
patent: 6096598 (2000-08-01), Furukawa et al.
patent: 6146938 (2000-11-01), Saida et al.
patent: 6165375 (2000-12-01), Yang et al.
patent: 6245612 (2001-06-01), Chang et al.
patent: 6281068 (2001-08-01), Cronel et al.
patent: 6315384 (2001-11-01), Ramaswami et al.
Lin Han Chih
Mao Hui Min
Tsai Tzu Ching
Birch & Stewart Kolasch & Birch, LLP
Nanya Technology Corporation
Trinh Michael
LandOfFree
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