Method of providing lower contact resistance in MOS transistor s

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 34, 437 45, 437131, 257281, 257409, 257410, 148DIG48, 148DIG82, H01L 21265

Patent

active

052963861

ABSTRACT:
Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

REFERENCES:
patent: 3725161 (1971-03-01), Kuper
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 4837173 (1989-06-01), Alvis et al.
patent: 4920076 (1990-04-01), Holland et al.
patent: 4983536 (1991-01-01), Bulat et al.
patent: 5019882 (1991-05-01), Solomon et al.
S. M. Sze, "Physics of semiconductor devices" (John Wiley & Sons, New York, 1981, 2nd Edition.) p. 29.
A. R. Srivatsa et al., "Nature of interfaces and oxidation processes in Ge.sup.+ -implanted Si" J. Appl. Phys. 65 4028 (1989).
D. Fathy, et al., "Formation of epitaxial layers of GE on Si substrates by GE implantation and oxidation" Appl. Phys. Lett. 51, 1337 (1987).
O. W. Holland, et al., "Novel oxidation process in GE.sup.+ -implanted Si and its effect on oxidation kinetics" Appl. PHys. Lett. 51, 520 (1987).
D. K. Sadana, et al., "Germanium implantation into silicon: an alternate pre-amorphization/rapid thermal annealing procedure for shallow junction technology" Mat. Res. Soc. Sym. Proc. 23, 303 (1984).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of providing lower contact resistance in MOS transistor s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of providing lower contact resistance in MOS transistor s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of providing lower contact resistance in MOS transistor s will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-436343

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.