Method of providing flexibility and alterability in VLSI gate ar

Details Method of providing flexibility and alterability in VLSI gate ar Method of providing flexibility and alterability in VLSI gate ar

1990-10-05

1992-02-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307441, 364491, H03K 19177

Patent

active

050878395

ABSTRACT:
A method and technique for inserting additive logic and flip-flops into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units internal to the chip by external signal injection.

REFERENCES:
patent: 4721868 (1988-01-01), Cornell et al.
patent: 4800302 (1989-01-01), Marum
patent: 4899067 (1990-02-01), So et al.
patent: 4908525 (1990-03-01), Yung
patent: 4987325 (1991-01-01), Seo
patent: 4990800 (1991-02-01), Lee

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