Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-04-28
2001-11-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S565000
Reexamination Certificate
active
06313683
ABSTRACT:
This application claims the benefit of European Application No. 98107883.5 filed Apr. 29, 1998, which is hereby incorporated by reference.
FIELD OF THE INVENTION
The invention relates to a method of providing clock signals to load circuits (FFS) in a ASIC device having a balanced clock tree system including a master clock line, for e.g. a clock trunk or H-tree system, and branched clock lines feeding the clock signals to the load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply clock signals.
The invention also relates to a method of providing clock signals to load circuits in a ASIC device having a plurality of balanced clock tree systems each including a master clock line, for example a clock trunk or H-tree system, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply clock signals.
Furthermore, the invention also relates to an ASIC device having a clock signal system for providing clock signals to load circuits in the ASIC device.
BACKGROUND OF THE INVENTION
There is a trend in the market for ASIC devices that are becoming more and more power-sensitive. As the geometries are becoming ever smaller, ASIC devices having more than 500 K gates are becoming the norm. Furthermore, there is a trend that the ASIC devices are incorporating ever more logic functions. Additionally, the frequencies of operation for such ASIC devices are also increasing. This, in turn, results in ASIC devices that consume more and more power. For such ASIC devices in the area of laptop computing and wireless communication as well as in many consumer products, the biggest cost factor nowadays is power consumption. Therefore, new designs of ASIC devices have to be developed in order to save power.
One way to save power is to turn off sections of the logic circuitry that are not active, and to allow the sections of the circuitry to be active only when needed. Among others, power can be saved by putting logic circuitry to a “sleep” mode with an interrupting mechanism to “wake up” the logic circuitry when needed or to run the different domains of the ASIC device with as slow clock frequencies as possible. The last mentioned possibility poses, however, the problem that the various clock signals having different frequencies have to be synchronized and such a synchronization is impaired by the skew effect which comes about because of the difference in time that the clock signals need to reach the flip flop which is nearest to the clock driver as compared to the time needed for the clock signals to arrive at the flip flop which is most distant from the clock driver.
As can be seen from the above, the distribution of clock signals is getting ever more important with increasing integration density and increasing clock rates in complex ASIC devices. Therefore, clock schemes, such as the single ended driver scheme, the double ended driver scheme, the local buffering scheme and the H-tree scheme, have been developed to assure, within a particular chip, that the skew on the clock signal lines does not exceed a maximum value which depends on the particular technology used.
The clock line network is the most critical network as concerns the design of the ASIC device. The fanout and the capacitive load related thereto is higher by two or three orders of magnitude as compared to such values in usual signal networks. Furthermore, the clock signal network extends generally across the hole surface of the chip, and the skew produced mainly by RC delays, has the effect that the clock signal is not synchronously provided at all the circuits which need the clock signal.
One has tried to solve the problem of the skew by providing an on-chip PLL circuit in the ASIC device itself to synchronize the various clock signals. In other words, in the prior art, each derived clock signal was generated asynchronously, and synchronization stages have been used to transfer the clock signals from one clock domain to another domain. However, this solution adds to the complexity of the ASIC device itself. Furthermore, the prior art solution is costly in terms of logic required and is not working in all the applications.
SUMMARY OF THE INVENTION
In view of the above, it is a main object of the invention to provide a method of distributing clock signals to load circuits in an ASIC device and to provide an ASIC device itself in which the method is implemented wherein the problem of skew is under control.
It is another object of the invention to provide a method of distributing clock signals to load circuits in an ASIC device and to provide an ASIC device itself in which the method is implemented wherein the clock signals for the domains of a clock system of the ASIC device are generated, distributed and routed in a synchronous manner irrespective of their frequency.
The method of distributing clock signals to FF-circuits in a ASIC device according to the invention comprises generating derived clock signals by gating the master clock signal which derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N) adapted to the need of the load circuits in a particular domain, and routing the master clock signal and/or derived clock signal for a particular domain to the load circuit of said domain whereby the clock signals are generated, distributed and routed in a synchronous manner.
In the method of the invention, all clock signals are generated from the same source, i.e. the master clock signal, and identical timing parameters for all submultiples of the master clock signal are provided by construction. Furthermore, all clock signals are synchronous by construction and the clock signals can be stopped synchronously without spikes to save power. The frequency of the clock signals may be varied on-the-fly in a synchronous manner. Furthermore, all derived clock signals can also be driven at one single frequency to improve scan- or testing efficiency.
In the method of the invention, a derived clock signal is defined as being a clock signal of a lower frequency, generated by gating out the necessary number of master clock cycles. The master clock signal and all derived clock signals will be generated from one single source, i.e. the master clock signal, and laid out as a signal clock net using BCT (balanced clock tree)-tools. By using a gating scheme for all clock signals, each clock domain can be driven at the lowest possible frequency thus reducing the power consumption. The master clock signal and all derived signals are synchronous such that the over all skew can be controlled. It is possible to generate for example a scan mode enable signal which will drive all loads at the same rate for scan testing, reducing test program overhead and complexity. Finally, only one IO(input/output)-driver is required and only one clock tree, for example a BCT- or an H-tree-system, will be inserted. Clock driver shielding in the IO-ring is necessary only for one clock signal instead of many different signals. These features entail a reduction of the amount of manual work needed to implement the clock systems.
According to an embodiment of the method of the invention, the gating is achieved by blanking out an appropriate number of master clock cycles using an enable signal which is generated for each clock domain. This method ensures that the derived clock signals are generated at the corresponding clock domains while minimizing skew.
According to an embodiment of the method of the invention, the enable signals are generated by using the falling edge of master clock pulses of the master clock signal. This has the advantage that the enable signals are also derived signals from the master clock pulses such that also the enable signals are synchronized with the master clock signals.
According to an embodiment of the method of the invention, the derived clock signals are generated by gating signals which start just after t
Ahner Bernd
Block Stefan
Mbouombouo Benjamin
Reuveni David
Cox Cassandra
LSI Logic Corporation
Tran Toan
Westman Champlin & Kelly PA
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