Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1976-09-08
1978-07-04
Pianalto, Bernard D.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
96 351, 156643, 427 35, 427 38, 427 43, 427 54, 427130, 427131, 427132, H01f 1000
Patent
active
040989178
ABSTRACT:
Method of providing a substrate with a patterned metal layer disposed thereon, wherein a patterned metal mask is employed in conjunction with ion milling to form the pattern in the metal layer on the substrate. The metal mask as contemplated herein is made of a metallic masking mterial taken from the group consisting of vanadium, tantalum, titanium, and a titanium-tungsten alloy--vanadium being a preferred material because of its resistance to erosion or etching from ion milling coupled with its relatively fast etch rate in a plasma atmosphere. This method has particular application to magnetic bubble domain technology, wherein successive layers of a magnetically soft material, vanadium, and photoresist are deposited on a magnetic film capable of supporting magnetic bubble domain propagation. The layer of magnetically soft material is typically permalloy, and upon being patterned in a selected configuration, defines a bubble propagation path on the magnetic bubble-supporting film. The photoresist layer is selectively exposed to the predetermined pattern by a source of energy, such as an E-beam, X-ray or ultra violet light. The portions of the vanadium layer exposed by the development of the patterned photoresist layer are then plasma etched to form a metal mask of the remaining vanadium layer. The remaining photoresist is then stripped, and the permalloy layer is then ion milled with the patterned vanadium layer serving as the mask. Thereafter, the remaining vanadium layer is removed by subjecting it to plasma etching.
REFERENCES:
patent: 3406043 (1968-10-01), Balde
patent: 3753814 (1973-08-01), Pulliam et al.
patent: 3808068 (1974-04-01), Johnson et al.
patent: 3900944 (1975-08-01), Fuller et al.
patent: 3904453 (1975-09-01), Revesv
Bullock David Carl
Shaikh Mohammed Sabir
Comfort James T.
Grossman Rene E.
Hiller William E.
Pianalto Bernard D.
Texas Instruments Incorporated
LandOfFree
Method of providing a patterned metal layer on a substrate emplo does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of providing a patterned metal layer on a substrate emplo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of providing a patterned metal layer on a substrate emplo will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-278315