Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-12-23
2004-11-23
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185020, C365S185230
Reexamination Certificate
active
06822899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention is related to semiconductor memory and in particular flash memory and the protection from data corruption during a fast power off.
2. Description of Related Art
A write operation for a flash memory comprises an erase phase followed by a program phase. Each of these phases requires time to complete, and if power is interrupted during a write operation, the data stored in the flash memory can be corrupted. In flash memories, such as a SONOS (Silicon Oxide Nitride Oxide Silicon) flash memory, the erase and program phases each take approximately 10 ms to complete. If the power voltage drops at a rate of approximately 1V/2 ms, then the programming operation will fail to complete.
In
FIG. 1
is shown a diagram of background art where an LVI (Low Voltage Inhibit circuit)
10
is used to detect when the chip voltage VDD drops below a predetermined voltage level and produce a signal
11
. When a protection circuit
12
receives the low voltage signal
11
from the LVI
10
circuit, the protection circuit produces a “switch to program” signal
13
to control a MUX
16
and go into the programming phase. The MUX
16
selects between a normal write mode
14
and an LVI write mode
15
, and switches to the LVI write mode upon receiving the “switch to program” signal
13
. A VBG register
20
drives a DAC
21
and a combination comparator and charge pump
22
to supply a programming voltage VNEG
23
to a memory bank
24
.
When the LVI circuit
10
detects a voltage drop during a write operation, the flash protection circuit
12
signals the MUX
16
to immediately go to a programming phase. If the LVI circuit
10
detects a voltage drop during the erase phase the circuitry switches to a program operation using old data currently being erased. If the voltage drop occurs during the programming phase, then the programming phase continues using new data in an attempt to complete the programming operation.
The problem with the technique describe for
FIG. 1
is that a programming operation takes time to complete, for instance 10 ms. Therefore, if a fast voltage drop at a rate of approximately 1V/2 ms or faster occurs, then the programming operation will fail to complete.
SUMMARY OF THE INVENTION
It is an objective of the present invention to switch to a fast programming operation when a flash memory power voltage drop is detected during a write operation.
It is another objective of the present invention to switch to a fast programming operation when a flash memory power voltage drop is detected during the erase phase using old data to program cells that were erased.
It is still another objective of the present invention to switch to a fast programming operation when the flash memory power voltage drop is detected during the programming phase using new data to program cells that have not been programmed.
It is yet another objective of the present invention to use a program voltage adjustment circuit to control the program voltage connected to the flash memory to a maximum value, speeding up the programming operation.
The present invention detects the drop in chip voltage and controls the programming voltage connected to a flash memory to be a maximum value to reduce the programming time. An LVI (low voltage inhibit circuit) detects the drop in power supply voltage and sends a signal to control an active write operation to switch into programming mode. At the same time the LVI circuit controls a programming adjustment circuit to cause the programming voltage to the flash memory to be a maximum value. The maximum value of the programming voltage dramatically reduces the programming time to eliminate the possibility that the programming operation will not complete before power is lost.
When the erase phase of a write operation is being carried out and the flash memory power drops, the LVI circuit controls the write phase to enter a programming phase using the old data being erased to program the memory cells not programmed and at the same time controls the programming voltage to be a maximum. When the programming phase is being carried out and the flash memory power voltage drops, the LVI circuit controls the write operation to remain in the programming phase using the new data that is being programmed and controls the programming voltage to be a maximum value to reduce programming time.
REFERENCES:
patent: 5444664 (1995-08-01), Kuroda et al.
patent: 5663918 (1997-09-01), Javanifard et al.
patent: 6552934 (2003-04-01), Roohparvar
Awong Carlos
Boulos Khaled
Shah Shailesh
Ackerman Stephen B.
Cypress Semiconductor Corporation
Nguyen Hien
Nguyen Van Thu
Sako Bradley T.
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