Method of protecting an integrated circuit, method of operating

Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive

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Details

361 56, 361 58, 361118, H02H 900

Patent

active

061045896

ABSTRACT:
The present invention includes integrated circuitry, an interface circuit of an integrated circuit device, cascode circuitry, method of protecting an integrated circuit, method of operating integrated circuitry, and method of operating cascode circuitry. One aspect of the present invention provides integrated circuitry including a driver adapted to couple with a pad and internal circuitry of an integrated circuit device, the driver includes a first transistor coupled with the pad; cascode circuitry including a second transistor coupled with the pad and a third transistor coupled with ground, the cascode circuitry configured to remain in an untriggered state during the presence of stress currents at the pad; and protection circuitry intermediate the pad and ground and configured to shunt stress currents from the pad to ground.

REFERENCES:
ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration, by Warren R. Anderson and David B. Krakauer, Electrical Overstress/Electrostatic Discharge Symposium--Oct. 6-8, 1998, 11 pages.

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